This file provides firmware functions to manage the following functionalities of the Reset and clock control (RCC) peripheral: More...

#include "stm32f4xx_rcc.h"

Macros
#define	RCC_OFFSET (RCC_BASE - PERIPH_BASE)

#define	CR_OFFSET (RCC_OFFSET + 0x00)

#define	HSION_BitNumber 0x00

#define	CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))

#define	CSSON_BitNumber 0x13

#define	CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))

#define	PLLON_BitNumber 0x18

#define	CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))

#define	PLLI2SON_BitNumber 0x1A

#define	CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))

#define	CFGR_OFFSET (RCC_OFFSET + 0x08)

#define	I2SSRC_BitNumber 0x17

#define	CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))

#define	BDCR_OFFSET (RCC_OFFSET + 0x70)

#define	RTCEN_BitNumber 0x0F

#define	BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))

#define	BDRST_BitNumber 0x10

#define	BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))

#define	CSR_OFFSET (RCC_OFFSET + 0x74)

#define	LSION_BitNumber 0x00

#define	CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))

#define	CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF)

#define	CFGR_MCO1_RESET_MASK ((uint32_t)0xF89FFFFF)

#define	FLAG_MASK ((uint8_t)0x1F)

#define	CR_BYTE3_ADDRESS ((uint32_t)0x40023802)

#define	CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))

#define	CIR_BYTE3_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))

#define	BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)

Functions
void	RCC_DeInit (void)
	Resets the RCC clock configuration to the default reset state. More...

void	RCC_HSEConfig (uint8_t RCC_HSE)
	Configures the External High Speed oscillator (HSE). More...

ErrorStatus	RCC_WaitForHSEStartUp (void)
	Waits for HSE start-up. More...

void	RCC_AdjustHSICalibrationValue (uint8_t HSICalibrationValue)
	Adjusts the Internal High Speed oscillator (HSI) calibration value. More...

void	RCC_HSICmd (FunctionalState NewState)
	Enables or disables the Internal High Speed oscillator (HSI). More...

void	RCC_LSEConfig (uint8_t RCC_LSE)
	Configures the External Low Speed oscillator (LSE). More...

void	RCC_LSICmd (FunctionalState NewState)
	Enables or disables the Internal Low Speed oscillator (LSI). More...

void	RCC_PLLConfig (uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)
	Configures the main PLL clock source, multiplication and division factors. More...

void	RCC_PLLCmd (FunctionalState NewState)
	Enables or disables the main PLL. More...

void	RCC_PLLI2SConfig (uint32_t PLLI2SN, uint32_t PLLI2SR)
	Configures the PLLI2S clock multiplication and division factors. More...

void	RCC_PLLI2SCmd (FunctionalState NewState)
	Enables or disables the PLLI2S. More...

void	RCC_ClockSecuritySystemCmd (FunctionalState NewState)
	Enables or disables the Clock Security System. More...

void	RCC_MCO1Config (uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
	Selects the clock source to output on MCO1 pin(PA8). More...

void	RCC_MCO2Config (uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
	Selects the clock source to output on MCO2 pin(PC9). More...

void	RCC_SYSCLKConfig (uint32_t RCC_SYSCLKSource)
	Configures the system clock (SYSCLK). More...

uint8_t	RCC_GetSYSCLKSource (void)
	Returns the clock source used as system clock. More...

void	RCC_HCLKConfig (uint32_t RCC_SYSCLK)
	Configures the AHB clock (HCLK). More...

void	RCC_PCLK1Config (uint32_t RCC_HCLK)
	Configures the Low Speed APB clock (PCLK1). More...

void	RCC_PCLK2Config (uint32_t RCC_HCLK)
	Configures the High Speed APB clock (PCLK2). More...

void	RCC_GetClocksFreq (RCC_ClocksTypeDef *RCC_Clocks)
	Returns the frequencies of different on chip clocks; SYSCLK, HCLK, PCLK1 and PCLK2. More...

void	RCC_RTCCLKConfig (uint32_t RCC_RTCCLKSource)
	Configures the RTC clock (RTCCLK). More...

void	RCC_RTCCLKCmd (FunctionalState NewState)
	Enables or disables the RTC clock. More...

void	RCC_BackupResetCmd (FunctionalState NewState)
	Forces or releases the Backup domain reset. More...

void	RCC_I2SCLKConfig (uint32_t RCC_I2SCLKSource)
	Configures the I2S clock source (I2SCLK). More...

void	RCC_AHB1PeriphClockCmd (uint32_t RCC_AHB1Periph, FunctionalState NewState)
	Enables or disables the AHB1 peripheral clock. More...

void	RCC_AHB2PeriphClockCmd (uint32_t RCC_AHB2Periph, FunctionalState NewState)
	Enables or disables the AHB2 peripheral clock. More...

void	RCC_AHB3PeriphClockCmd (uint32_t RCC_AHB3Periph, FunctionalState NewState)
	Enables or disables the AHB3 peripheral clock. More...

void	RCC_APB1PeriphClockCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
	Enables or disables the Low Speed APB (APB1) peripheral clock. More...

void	RCC_APB2PeriphClockCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
	Enables or disables the High Speed APB (APB2) peripheral clock. More...

void	RCC_AHB1PeriphResetCmd (uint32_t RCC_AHB1Periph, FunctionalState NewState)
	Forces or releases AHB1 peripheral reset. More...

void	RCC_AHB2PeriphResetCmd (uint32_t RCC_AHB2Periph, FunctionalState NewState)
	Forces or releases AHB2 peripheral reset. More...

void	RCC_AHB3PeriphResetCmd (uint32_t RCC_AHB3Periph, FunctionalState NewState)
	Forces or releases AHB3 peripheral reset. More...

void	RCC_APB1PeriphResetCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
	Forces or releases Low Speed APB (APB1) peripheral reset. More...

void	RCC_APB2PeriphResetCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
	Forces or releases High Speed APB (APB2) peripheral reset. More...

void	RCC_AHB1PeriphClockLPModeCmd (uint32_t RCC_AHB1Periph, FunctionalState NewState)
	Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. More...

void	RCC_AHB2PeriphClockLPModeCmd (uint32_t RCC_AHB2Periph, FunctionalState NewState)
	Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode. More...

void	RCC_AHB3PeriphClockLPModeCmd (uint32_t RCC_AHB3Periph, FunctionalState NewState)
	Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode. More...

void	RCC_APB1PeriphClockLPModeCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
	Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. More...

void	RCC_APB2PeriphClockLPModeCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
	Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. More...

void	RCC_ITConfig (uint8_t RCC_IT, FunctionalState NewState)
	Enables or disables the specified RCC interrupts. More...

FlagStatus	RCC_GetFlagStatus (uint8_t RCC_FLAG)
	Checks whether the specified RCC flag is set or not. More...

void	RCC_ClearFlag (void)
	Clears the RCC reset flags. The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST. More...

ITStatus	RCC_GetITStatus (uint8_t RCC_IT)
	Checks whether the specified RCC interrupt has occurred or not. More...

void	RCC_ClearITPendingBit (uint8_t RCC_IT)
	Clears the RCC's interrupt pending bits. More...

Detailed Description

This file provides firmware functions to manage the following functionalities of the Reset and clock control (RCC) peripheral:

Author: MCD Application Team

Version: V1.0.2

Date

05-March-2012

Internal/external clocks, PLL, CSS and MCO configuration
System, AHB and APB busses clocks configuration
Peripheral clocks configuration
Interrupts and flags management

*               
*          ===================================================================
*                               RCC specific features
*          ===================================================================
*    
*          After reset the device is running from Internal High Speed oscillator 
*          (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache 
*          and I-Cache are disabled, and all peripherals are off except internal
*          SRAM, Flash and JTAG.
*           - There is no prescaler on High speed (AHB) and Low speed (APB) busses;
*             all peripherals mapped on these busses are running at HSI speed.
*             - The clock for all peripherals is switched off, except the SRAM and FLASH.
*           - All GPIOs are in input floating state, except the JTAG pins which
*             are assigned to be used for debug purpose.
*        
*          Once the device started from reset, the user application has to:        
*           - Configure the clock source to be used to drive the System clock
*             (if the application needs higher frequency/performance)
*           - Configure the System clock frequency and Flash settings  
*           - Configure the AHB and APB busses prescalers
*           - Enable the clock for the peripheral(s) to be used
*           - Configure the clock source(s) for peripherals which clocks are not
*             derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)      
*                        
*

Attention

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

   http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Macros

Functions

Detailed Description

© COPYRIGHT 2012 STMicroelectronics