STM32F4 Standard Peripheral bibliotheek  1.0
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stm32f4xx_rcc.h
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1 
28 /* Define to prevent recursive inclusion -------------------------------------*/
29 #ifndef __STM32F4xx_RCC_H
30 #define __STM32F4xx_RCC_H
31 
32 #ifdef __cplusplus
33  extern "C" {
34 #endif
35 
36 /* Includes ------------------------------------------------------------------*/
37 #include "stm32f4xx.h"
38 
47 /* Exported types ------------------------------------------------------------*/
48 typedef struct
49 {
50  uint32_t SYSCLK_Frequency;
51  uint32_t HCLK_Frequency;
52  uint32_t PCLK1_Frequency;
53  uint32_t PCLK2_Frequency;
54 }RCC_ClocksTypeDef;
55 
56 /* Exported constants --------------------------------------------------------*/
57 
65 #define RCC_HSE_OFF ((uint8_t)0x00)
66 #define RCC_HSE_ON ((uint8_t)0x01)
67 #define RCC_HSE_Bypass ((uint8_t)0x05)
68 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
69  ((HSE) == RCC_HSE_Bypass))
70 
77 #define RCC_PLLSource_HSI ((uint32_t)0x00000000)
78 #define RCC_PLLSource_HSE ((uint32_t)0x00400000)
79 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \
80  ((SOURCE) == RCC_PLLSource_HSE))
81 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
82 #define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
83 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
84 #define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
85 
86 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
87 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
88 
95 #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
96 #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
97 #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
98 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
99  ((SOURCE) == RCC_SYSCLKSource_HSE) || \
100  ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
101 
108 #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
109 #define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
110 #define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
111 #define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
112 #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
113 #define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
114 #define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
115 #define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
116 #define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
117 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
118  ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
119  ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
120  ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
121  ((HCLK) == RCC_SYSCLK_Div512))
122 
129 #define RCC_HCLK_Div1 ((uint32_t)0x00000000)
130 #define RCC_HCLK_Div2 ((uint32_t)0x00001000)
131 #define RCC_HCLK_Div4 ((uint32_t)0x00001400)
132 #define RCC_HCLK_Div8 ((uint32_t)0x00001800)
133 #define RCC_HCLK_Div16 ((uint32_t)0x00001C00)
134 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
135  ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
136  ((PCLK) == RCC_HCLK_Div16))
137 
144 #define RCC_IT_LSIRDY ((uint8_t)0x01)
145 #define RCC_IT_LSERDY ((uint8_t)0x02)
146 #define RCC_IT_HSIRDY ((uint8_t)0x04)
147 #define RCC_IT_HSERDY ((uint8_t)0x08)
148 #define RCC_IT_PLLRDY ((uint8_t)0x10)
149 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
150 #define RCC_IT_CSS ((uint8_t)0x80)
151 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))
152 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
153  ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
154  ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
155  ((IT) == RCC_IT_PLLI2SRDY))
156 #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))
157 
164 #define RCC_LSE_OFF ((uint8_t)0x00)
165 #define RCC_LSE_ON ((uint8_t)0x01)
166 #define RCC_LSE_Bypass ((uint8_t)0x04)
167 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
168  ((LSE) == RCC_LSE_Bypass))
169 
176 #define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
177 #define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
178 #define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300)
179 #define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300)
180 #define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300)
181 #define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300)
182 #define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300)
183 #define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300)
184 #define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300)
185 #define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300)
186 #define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300)
187 #define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300)
188 #define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300)
189 #define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300)
190 #define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300)
191 #define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300)
192 #define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300)
193 #define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300)
194 #define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300)
195 #define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300)
196 #define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300)
197 #define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300)
198 #define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300)
199 #define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300)
200 #define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300)
201 #define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300)
202 #define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300)
203 #define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300)
204 #define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300)
205 #define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300)
206 #define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300)
207 #define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300)
208 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
209  ((SOURCE) == RCC_RTCCLKSource_LSI) || \
210  ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \
211  ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \
212  ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \
213  ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \
214  ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \
215  ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \
216  ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \
217  ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \
218  ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \
219  ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \
220  ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \
221  ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \
222  ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \
223  ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \
224  ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \
225  ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \
226  ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \
227  ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \
228  ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \
229  ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \
230  ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \
231  ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \
232  ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \
233  ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \
234  ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \
235  ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \
236  ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \
237  ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \
238  ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \
239  ((SOURCE) == RCC_RTCCLKSource_HSE_Div31))
240 
247 #define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00)
248 #define RCC_I2S2CLKSource_Ext ((uint8_t)0x01)
249 
250 #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext))
251 
258 #define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001)
259 #define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002)
260 #define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004)
261 #define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008)
262 #define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010)
263 #define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020)
264 #define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040)
265 #define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080)
266 #define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100)
267 #define RCC_AHB1Periph_CRC ((uint32_t)0x00001000)
268 #define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000)
269 #define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000)
270 #define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000)
271 #define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000)
272 #define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000)
273 #define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000)
274 #define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000)
275 #define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000)
276 #define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000)
277 #define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000)
278 #define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000)
279 #define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000)
280 #define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000)
281 #define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x818BEE00) == 0x00) && ((PERIPH) != 0x00))
282 #define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD9FEE00) == 0x00) && ((PERIPH) != 0x00))
283 #define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81986E00) == 0x00) && ((PERIPH) != 0x00))
284 
291 #define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001)
292 #define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010)
293 #define RCC_AHB2Periph_HASH ((uint32_t)0x00000020)
294 #define RCC_AHB2Periph_RNG ((uint32_t)0x00000040)
295 #define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080)
296 #define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00))
297 
304 #define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001)
305 #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
306 
313 #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
314 #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
315 #define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
316 #define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
317 #define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
318 #define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
319 #define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)
320 #define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
321 #define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
322 #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
323 #define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
324 #define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
325 #define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
326 #define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
327 #define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
328 #define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
329 #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
330 #define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
331 #define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000)
332 #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
333 #define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
334 #define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
335 #define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
336 #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC9013600) == 0x00) && ((PERIPH) != 0x00))
337 
344 #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001)
345 #define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002)
346 #define RCC_APB2Periph_USART1 ((uint32_t)0x00000010)
347 #define RCC_APB2Periph_USART6 ((uint32_t)0x00000020)
348 #define RCC_APB2Periph_ADC ((uint32_t)0x00000100)
349 #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100)
350 #define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200)
351 #define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400)
352 #define RCC_APB2Periph_SDIO ((uint32_t)0x00000800)
353 #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
354 #define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000)
355 #define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000)
356 #define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000)
357 #define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000)
358 #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A0CC) == 0x00) && ((PERIPH) != 0x00))
359 #define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A6CC) == 0x00) && ((PERIPH) != 0x00))
360 
367 #define RCC_MCO1Source_HSI ((uint32_t)0x00000000)
368 #define RCC_MCO1Source_LSE ((uint32_t)0x00200000)
369 #define RCC_MCO1Source_HSE ((uint32_t)0x00400000)
370 #define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000)
371 #define RCC_MCO1Div_1 ((uint32_t)0x00000000)
372 #define RCC_MCO1Div_2 ((uint32_t)0x04000000)
373 #define RCC_MCO1Div_3 ((uint32_t)0x05000000)
374 #define RCC_MCO1Div_4 ((uint32_t)0x06000000)
375 #define RCC_MCO1Div_5 ((uint32_t)0x07000000)
376 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \
377  ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK))
378 
379 #define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \
380  ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \
381  ((DIV) == RCC_MCO1Div_5))
382 
389 #define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000)
390 #define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000)
391 #define RCC_MCO2Source_HSE ((uint32_t)0x80000000)
392 #define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000)
393 #define RCC_MCO2Div_1 ((uint32_t)0x00000000)
394 #define RCC_MCO2Div_2 ((uint32_t)0x20000000)
395 #define RCC_MCO2Div_3 ((uint32_t)0x28000000)
396 #define RCC_MCO2Div_4 ((uint32_t)0x30000000)
397 #define RCC_MCO2Div_5 ((uint32_t)0x38000000)
398 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \
399  ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK))
400 
401 #define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \
402  ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \
403  ((DIV) == RCC_MCO2Div_5))
404 
411 #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
412 #define RCC_FLAG_HSERDY ((uint8_t)0x31)
413 #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
414 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
415 #define RCC_FLAG_LSERDY ((uint8_t)0x41)
416 #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
417 #define RCC_FLAG_BORRST ((uint8_t)0x79)
418 #define RCC_FLAG_PINRST ((uint8_t)0x7A)
419 #define RCC_FLAG_PORRST ((uint8_t)0x7B)
420 #define RCC_FLAG_SFTRST ((uint8_t)0x7C)
421 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
422 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
423 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
424 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
425  ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
426  ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \
427  ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
428  ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
429  ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
430  ((FLAG) == RCC_FLAG_PLLI2SRDY))
431 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
432 
440 /* Exported macro ------------------------------------------------------------*/
441 /* Exported functions --------------------------------------------------------*/
442 
443 /* Function used to set the RCC clock configuration to the default reset state */
444 void RCC_DeInit(void);
445 
446 /* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
447 void RCC_HSEConfig(uint8_t RCC_HSE);
448 ErrorStatus RCC_WaitForHSEStartUp(void);
449 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
450 void RCC_HSICmd(FunctionalState NewState);
451 void RCC_LSEConfig(uint8_t RCC_LSE);
452 void RCC_LSICmd(FunctionalState NewState);
453 
454 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ);
455 void RCC_PLLCmd(FunctionalState NewState);
456 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR);
457 void RCC_PLLI2SCmd(FunctionalState NewState);
458 
459 void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
460 void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);
461 void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);
462 
463 /* System, AHB and APB busses clocks configuration functions ******************/
464 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
465 uint8_t RCC_GetSYSCLKSource(void);
466 void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
467 void RCC_PCLK1Config(uint32_t RCC_HCLK);
468 void RCC_PCLK2Config(uint32_t RCC_HCLK);
469 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
470 
471 /* Peripheral clocks configuration functions **********************************/
472 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
473 void RCC_RTCCLKCmd(FunctionalState NewState);
474 void RCC_BackupResetCmd(FunctionalState NewState);
475 void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
476 
477 void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
478 void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
479 void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
480 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
481 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
482 
483 void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
484 void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
485 void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
486 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
487 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
488 
489 void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
490 void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
491 void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
492 void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
493 void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
494 
495 /* Interrupts and flags management functions **********************************/
496 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
497 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
498 void RCC_ClearFlag(void);
499 ITStatus RCC_GetITStatus(uint8_t RCC_IT);
500 void RCC_ClearITPendingBit(uint8_t RCC_IT);
501 
502 #ifdef __cplusplus
503 }
504 #endif
505 
506 #endif /* __STM32F4xx_RCC_H */
507 
516 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/