STM32F4 Standard Peripheral bibliotheek  1.0
ST Microelectronics bibliotheek documentatie voor de STM32F4 Standard Peripheral Library
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Modules | Data Structures | Macros | Functions
RCC
STM32F4xx_StdPeriph_Driver

RCC driver modules. More...

Modules

 RCC_Exported_Constants
 
 RCC_Private_Functions
 

Data Structures

struct  RCC_ClocksTypeDef
 

Macros

#define RCC_OFFSET   (RCC_BASE - PERIPH_BASE)
 
#define CR_OFFSET   (RCC_OFFSET + 0x00)
 
#define HSION_BitNumber   0x00
 
#define CR_HSION_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
 
#define CSSON_BitNumber   0x13
 
#define CR_CSSON_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
 
#define PLLON_BitNumber   0x18
 
#define CR_PLLON_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
 
#define PLLI2SON_BitNumber   0x1A
 
#define CR_PLLI2SON_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
 
#define CFGR_OFFSET   (RCC_OFFSET + 0x08)
 
#define I2SSRC_BitNumber   0x17
 
#define CFGR_I2SSRC_BB   (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
 
#define BDCR_OFFSET   (RCC_OFFSET + 0x70)
 
#define RTCEN_BitNumber   0x0F
 
#define BDCR_RTCEN_BB   (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
 
#define BDRST_BitNumber   0x10
 
#define BDCR_BDRST_BB   (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
 
#define CSR_OFFSET   (RCC_OFFSET + 0x74)
 
#define LSION_BitNumber   0x00
 
#define CSR_LSION_BB   (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
 
#define CFGR_MCO2_RESET_MASK   ((uint32_t)0x07FFFFFF)
 
#define CFGR_MCO1_RESET_MASK   ((uint32_t)0xF89FFFFF)
 
#define FLAG_MASK   ((uint8_t)0x1F)
 
#define CR_BYTE3_ADDRESS   ((uint32_t)0x40023802)
 
#define CIR_BYTE2_ADDRESS   ((uint32_t)(RCC_BASE + 0x0C + 0x01))
 
#define CIR_BYTE3_ADDRESS   ((uint32_t)(RCC_BASE + 0x0C + 0x02))
 
#define BDCR_ADDRESS   (PERIPH_BASE + BDCR_OFFSET)
 

Functions

void RCC_DeInit (void)
 Resets the RCC clock configuration to the default reset state. More...
 
void RCC_HSEConfig (uint8_t RCC_HSE)
 Configures the External High Speed oscillator (HSE). More...
 
ErrorStatus RCC_WaitForHSEStartUp (void)
 Waits for HSE start-up. More...
 
void RCC_AdjustHSICalibrationValue (uint8_t HSICalibrationValue)
 Adjusts the Internal High Speed oscillator (HSI) calibration value. More...
 
void RCC_HSICmd (FunctionalState NewState)
 Enables or disables the Internal High Speed oscillator (HSI). More...
 
void RCC_LSEConfig (uint8_t RCC_LSE)
 Configures the External Low Speed oscillator (LSE). More...
 
void RCC_LSICmd (FunctionalState NewState)
 Enables or disables the Internal Low Speed oscillator (LSI). More...
 
void RCC_PLLConfig (uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)
 Configures the main PLL clock source, multiplication and division factors. More...
 
void RCC_PLLCmd (FunctionalState NewState)
 Enables or disables the main PLL. More...
 
void RCC_PLLI2SConfig (uint32_t PLLI2SN, uint32_t PLLI2SR)
 Configures the PLLI2S clock multiplication and division factors. More...
 
void RCC_PLLI2SCmd (FunctionalState NewState)
 Enables or disables the PLLI2S. More...
 
void RCC_ClockSecuritySystemCmd (FunctionalState NewState)
 Enables or disables the Clock Security System. More...
 
void RCC_MCO1Config (uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
 Selects the clock source to output on MCO1 pin(PA8). More...
 
void RCC_MCO2Config (uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
 Selects the clock source to output on MCO2 pin(PC9). More...
 
void RCC_SYSCLKConfig (uint32_t RCC_SYSCLKSource)
 Configures the system clock (SYSCLK). More...
 
uint8_t RCC_GetSYSCLKSource (void)
 Returns the clock source used as system clock. More...
 
void RCC_HCLKConfig (uint32_t RCC_SYSCLK)
 Configures the AHB clock (HCLK). More...
 
void RCC_PCLK1Config (uint32_t RCC_HCLK)
 Configures the Low Speed APB clock (PCLK1). More...
 
void RCC_PCLK2Config (uint32_t RCC_HCLK)
 Configures the High Speed APB clock (PCLK2). More...
 
void RCC_GetClocksFreq (RCC_ClocksTypeDef *RCC_Clocks)
 Returns the frequencies of different on chip clocks; SYSCLK, HCLK, PCLK1 and PCLK2. More...
 
void RCC_RTCCLKConfig (uint32_t RCC_RTCCLKSource)
 Configures the RTC clock (RTCCLK). More...
 
void RCC_RTCCLKCmd (FunctionalState NewState)
 Enables or disables the RTC clock. More...
 
void RCC_BackupResetCmd (FunctionalState NewState)
 Forces or releases the Backup domain reset. More...
 
void RCC_I2SCLKConfig (uint32_t RCC_I2SCLKSource)
 Configures the I2S clock source (I2SCLK). More...
 
void RCC_AHB1PeriphClockCmd (uint32_t RCC_AHB1Periph, FunctionalState NewState)
 Enables or disables the AHB1 peripheral clock. More...
 
void RCC_AHB2PeriphClockCmd (uint32_t RCC_AHB2Periph, FunctionalState NewState)
 Enables or disables the AHB2 peripheral clock. More...
 
void RCC_AHB3PeriphClockCmd (uint32_t RCC_AHB3Periph, FunctionalState NewState)
 Enables or disables the AHB3 peripheral clock. More...
 
void RCC_APB1PeriphClockCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
 Enables or disables the Low Speed APB (APB1) peripheral clock. More...
 
void RCC_APB2PeriphClockCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
 Enables or disables the High Speed APB (APB2) peripheral clock. More...
 
void RCC_AHB1PeriphResetCmd (uint32_t RCC_AHB1Periph, FunctionalState NewState)
 Forces or releases AHB1 peripheral reset. More...
 
void RCC_AHB2PeriphResetCmd (uint32_t RCC_AHB2Periph, FunctionalState NewState)
 Forces or releases AHB2 peripheral reset. More...
 
void RCC_AHB3PeriphResetCmd (uint32_t RCC_AHB3Periph, FunctionalState NewState)
 Forces or releases AHB3 peripheral reset. More...
 
void RCC_APB1PeriphResetCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
 Forces or releases Low Speed APB (APB1) peripheral reset. More...
 
void RCC_APB2PeriphResetCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
 Forces or releases High Speed APB (APB2) peripheral reset. More...
 
void RCC_AHB1PeriphClockLPModeCmd (uint32_t RCC_AHB1Periph, FunctionalState NewState)
 Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. More...
 
void RCC_AHB2PeriphClockLPModeCmd (uint32_t RCC_AHB2Periph, FunctionalState NewState)
 Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode. More...
 
void RCC_AHB3PeriphClockLPModeCmd (uint32_t RCC_AHB3Periph, FunctionalState NewState)
 Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode. More...
 
void RCC_APB1PeriphClockLPModeCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
 Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. More...
 
void RCC_APB2PeriphClockLPModeCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
 Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. More...
 
void RCC_ITConfig (uint8_t RCC_IT, FunctionalState NewState)
 Enables or disables the specified RCC interrupts. More...
 
FlagStatus RCC_GetFlagStatus (uint8_t RCC_FLAG)
 Checks whether the specified RCC flag is set or not. More...
 
void RCC_ClearFlag (void)
 Clears the RCC reset flags. The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST. More...
 
ITStatus RCC_GetITStatus (uint8_t RCC_IT)
 Checks whether the specified RCC interrupt has occurred or not. More...
 
void RCC_ClearITPendingBit (uint8_t RCC_IT)
 Clears the RCC's interrupt pending bits. More...
 

Detailed Description

RCC driver modules.

Function Documentation

void RCC_AdjustHSICalibrationValue ( uint8_t  HSICalibrationValue)

Adjusts the Internal High Speed oscillator (HSI) calibration value.

Note
The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal HSI RC.
Parameters
HSICalibrationValue,:specifies the calibration trimming value. This parameter must be a number between 0 and 0x1F.
Return values
None
void RCC_AHB1PeriphClockCmd ( uint32_t  RCC_AHB1Periph,
FunctionalState  NewState 
)

Enables or disables the AHB1 peripheral clock.

Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Parameters
RCC_AHBPeriph,:specifies the AHB1 peripheral to gates its clock. This parameter can be any combination of the following values:
  • RCC_AHB1Periph_GPIOA: GPIOA clock
  • RCC_AHB1Periph_GPIOB: GPIOB clock
  • RCC_AHB1Periph_GPIOC: GPIOC clock
  • RCC_AHB1Periph_GPIOD: GPIOD clock
  • RCC_AHB1Periph_GPIOE: GPIOE clock
  • RCC_AHB1Periph_GPIOF: GPIOF clock
  • RCC_AHB1Periph_GPIOG: GPIOG clock
  • RCC_AHB1Periph_GPIOG: GPIOG clock
  • RCC_AHB1Periph_GPIOI: GPIOI clock
  • RCC_AHB1Periph_CRC: CRC clock
  • RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
  • RCC_AHB1Periph_CCMDATARAMEN CCM data RAM interface clock
  • RCC_AHB1Periph_DMA1: DMA1 clock
  • RCC_AHB1Periph_DMA2: DMA2 clock
  • RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
  • RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
  • RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
  • RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
  • RCC_AHB1Periph_OTG_HS: USB OTG HS clock
  • RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
NewState,:new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values
None
void RCC_AHB1PeriphClockLPModeCmd ( uint32_t  RCC_AHB1Periph,
FunctionalState  NewState 
)

Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.

Note
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.
Parameters
RCC_AHBPeriph,:specifies the AHB1 peripheral to gates its clock. This parameter can be any combination of the following values:
  • RCC_AHB1Periph_GPIOA: GPIOA clock
  • RCC_AHB1Periph_GPIOB: GPIOB clock
  • RCC_AHB1Periph_GPIOC: GPIOC clock
  • RCC_AHB1Periph_GPIOD: GPIOD clock
  • RCC_AHB1Periph_GPIOE: GPIOE clock
  • RCC_AHB1Periph_GPIOF: GPIOF clock
  • RCC_AHB1Periph_GPIOG: GPIOG clock
  • RCC_AHB1Periph_GPIOG: GPIOG clock
  • RCC_AHB1Periph_GPIOI: GPIOI clock
  • RCC_AHB1Periph_CRC: CRC clock
  • RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
  • RCC_AHB1Periph_DMA1: DMA1 clock
  • RCC_AHB1Periph_DMA2: DMA2 clock
  • RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
  • RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
  • RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
  • RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
  • RCC_AHB1Periph_OTG_HS: USB OTG HS clock
  • RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
NewState,:new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values
None
void RCC_AHB1PeriphResetCmd ( uint32_t  RCC_AHB1Periph,
FunctionalState  NewState 
)

Forces or releases AHB1 peripheral reset.

Parameters
RCC_AHB1Periph,:specifies the AHB1 peripheral to reset. This parameter can be any combination of the following values:
  • RCC_AHB1Periph_GPIOA: GPIOA clock
  • RCC_AHB1Periph_GPIOB: GPIOB clock
  • RCC_AHB1Periph_GPIOC: GPIOC clock
  • RCC_AHB1Periph_GPIOD: GPIOD clock
  • RCC_AHB1Periph_GPIOE: GPIOE clock
  • RCC_AHB1Periph_GPIOF: GPIOF clock
  • RCC_AHB1Periph_GPIOG: GPIOG clock
  • RCC_AHB1Periph_GPIOG: GPIOG clock
  • RCC_AHB1Periph_GPIOI: GPIOI clock
  • RCC_AHB1Periph_CRC: CRC clock
  • RCC_AHB1Periph_DMA1: DMA1 clock
  • RCC_AHB1Periph_DMA2: DMA2 clock
  • RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
  • RCC_AHB1Periph_OTG_HS: USB OTG HS clock
NewState,:new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
Return values
None
void RCC_AHB2PeriphClockCmd ( uint32_t  RCC_AHB2Periph,
FunctionalState  NewState 
)

Enables or disables the AHB2 peripheral clock.

Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Parameters
RCC_AHBPeriph,:specifies the AHB2 peripheral to gates its clock. This parameter can be any combination of the following values:
  • RCC_AHB2Periph_DCMI: DCMI clock
  • RCC_AHB2Periph_CRYP: CRYP clock
  • RCC_AHB2Periph_HASH: HASH clock
  • RCC_AHB2Periph_RNG: RNG clock
  • RCC_AHB2Periph_OTG_FS: USB OTG FS clock
NewState,:new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values
None
void RCC_AHB2PeriphClockLPModeCmd ( uint32_t  RCC_AHB2Periph,
FunctionalState  NewState 
)

Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode.

Note
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.
Parameters
RCC_AHBPeriph,:specifies the AHB2 peripheral to gates its clock. This parameter can be any combination of the following values:
  • RCC_AHB2Periph_DCMI: DCMI clock
  • RCC_AHB2Periph_CRYP: CRYP clock
  • RCC_AHB2Periph_HASH: HASH clock
  • RCC_AHB2Periph_RNG: RNG clock
  • RCC_AHB2Periph_OTG_FS: USB OTG FS clock
NewState,:new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values
None
void RCC_AHB2PeriphResetCmd ( uint32_t  RCC_AHB2Periph,
FunctionalState  NewState 
)

Forces or releases AHB2 peripheral reset.

Parameters
RCC_AHB2Periph,:specifies the AHB2 peripheral to reset. This parameter can be any combination of the following values:
  • RCC_AHB2Periph_DCMI: DCMI clock
  • RCC_AHB2Periph_CRYP: CRYP clock
  • RCC_AHB2Periph_HASH: HASH clock
  • RCC_AHB2Periph_RNG: RNG clock
  • RCC_AHB2Periph_OTG_FS: USB OTG FS clock
NewState,:new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
Return values
None
void RCC_AHB3PeriphClockCmd ( uint32_t  RCC_AHB3Periph,
FunctionalState  NewState 
)

Enables or disables the AHB3 peripheral clock.

Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Parameters
RCC_AHBPeriph,:specifies the AHB3 peripheral to gates its clock. This parameter must be: RCC_AHB3Periph_FSMC
NewState,:new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values
None
void RCC_AHB3PeriphClockLPModeCmd ( uint32_t  RCC_AHB3Periph,
FunctionalState  NewState 
)

Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.

Note
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.
Parameters
RCC_AHBPeriph,:specifies the AHB3 peripheral to gates its clock. This parameter must be: RCC_AHB3Periph_FSMC
NewState,:new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values
None
void RCC_AHB3PeriphResetCmd ( uint32_t  RCC_AHB3Periph,
FunctionalState  NewState 
)

Forces or releases AHB3 peripheral reset.

Parameters
RCC_AHB3Periph,:specifies the AHB3 peripheral to reset. This parameter must be: RCC_AHB3Periph_FSMC
NewState,:new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
Return values
None
void RCC_APB1PeriphClockCmd ( uint32_t  RCC_APB1Periph,
FunctionalState  NewState 
)

Enables or disables the Low Speed APB (APB1) peripheral clock.

Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Parameters
RCC_APB1Periph,:specifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values:
  • RCC_APB1Periph_TIM2: TIM2 clock
  • RCC_APB1Periph_TIM3: TIM3 clock
  • RCC_APB1Periph_TIM4: TIM4 clock
  • RCC_APB1Periph_TIM5: TIM5 clock
  • RCC_APB1Periph_TIM6: TIM6 clock
  • RCC_APB1Periph_TIM7: TIM7 clock
  • RCC_APB1Periph_TIM12: TIM12 clock
  • RCC_APB1Periph_TIM13: TIM13 clock
  • RCC_APB1Periph_TIM14: TIM14 clock
  • RCC_APB1Periph_WWDG: WWDG clock
  • RCC_APB1Periph_SPI2: SPI2 clock
  • RCC_APB1Periph_SPI3: SPI3 clock
  • RCC_APB1Periph_USART2: USART2 clock
  • RCC_APB1Periph_USART3: USART3 clock
  • RCC_APB1Periph_UART4: UART4 clock
  • RCC_APB1Periph_UART5: UART5 clock
  • RCC_APB1Periph_I2C1: I2C1 clock
  • RCC_APB1Periph_I2C2: I2C2 clock
  • RCC_APB1Periph_I2C3: I2C3 clock
  • RCC_APB1Periph_CAN1: CAN1 clock
  • RCC_APB1Periph_CAN2: CAN2 clock
  • RCC_APB1Periph_PWR: PWR clock
  • RCC_APB1Periph_DAC: DAC clock
NewState,:new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values
None
void RCC_APB1PeriphClockLPModeCmd ( uint32_t  RCC_APB1Periph,
FunctionalState  NewState 
)

Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.

Note
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.
Parameters
RCC_APB1Periph,:specifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values:
  • RCC_APB1Periph_TIM2: TIM2 clock
  • RCC_APB1Periph_TIM3: TIM3 clock
  • RCC_APB1Periph_TIM4: TIM4 clock
  • RCC_APB1Periph_TIM5: TIM5 clock
  • RCC_APB1Periph_TIM6: TIM6 clock
  • RCC_APB1Periph_TIM7: TIM7 clock
  • RCC_APB1Periph_TIM12: TIM12 clock
  • RCC_APB1Periph_TIM13: TIM13 clock
  • RCC_APB1Periph_TIM14: TIM14 clock
  • RCC_APB1Periph_WWDG: WWDG clock
  • RCC_APB1Periph_SPI2: SPI2 clock
  • RCC_APB1Periph_SPI3: SPI3 clock
  • RCC_APB1Periph_USART2: USART2 clock
  • RCC_APB1Periph_USART3: USART3 clock
  • RCC_APB1Periph_UART4: UART4 clock
  • RCC_APB1Periph_UART5: UART5 clock
  • RCC_APB1Periph_I2C1: I2C1 clock
  • RCC_APB1Periph_I2C2: I2C2 clock
  • RCC_APB1Periph_I2C3: I2C3 clock
  • RCC_APB1Periph_CAN1: CAN1 clock
  • RCC_APB1Periph_CAN2: CAN2 clock
  • RCC_APB1Periph_PWR: PWR clock
  • RCC_APB1Periph_DAC: DAC clock
NewState,:new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values
None
void RCC_APB1PeriphResetCmd ( uint32_t  RCC_APB1Periph,
FunctionalState  NewState 
)

Forces or releases Low Speed APB (APB1) peripheral reset.

Parameters
RCC_APB1Periph,:specifies the APB1 peripheral to reset. This parameter can be any combination of the following values:
  • RCC_APB1Periph_TIM2: TIM2 clock
  • RCC_APB1Periph_TIM3: TIM3 clock
  • RCC_APB1Periph_TIM4: TIM4 clock
  • RCC_APB1Periph_TIM5: TIM5 clock
  • RCC_APB1Periph_TIM6: TIM6 clock
  • RCC_APB1Periph_TIM7: TIM7 clock
  • RCC_APB1Periph_TIM12: TIM12 clock
  • RCC_APB1Periph_TIM13: TIM13 clock
  • RCC_APB1Periph_TIM14: TIM14 clock
  • RCC_APB1Periph_WWDG: WWDG clock
  • RCC_APB1Periph_SPI2: SPI2 clock
  • RCC_APB1Periph_SPI3: SPI3 clock
  • RCC_APB1Periph_USART2: USART2 clock
  • RCC_APB1Periph_USART3: USART3 clock
  • RCC_APB1Periph_UART4: UART4 clock
  • RCC_APB1Periph_UART5: UART5 clock
  • RCC_APB1Periph_I2C1: I2C1 clock
  • RCC_APB1Periph_I2C2: I2C2 clock
  • RCC_APB1Periph_I2C3: I2C3 clock
  • RCC_APB1Periph_CAN1: CAN1 clock
  • RCC_APB1Periph_CAN2: CAN2 clock
  • RCC_APB1Periph_PWR: PWR clock
  • RCC_APB1Periph_DAC: DAC clock
NewState,:new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
Return values
None
void RCC_APB2PeriphClockCmd ( uint32_t  RCC_APB2Periph,
FunctionalState  NewState 
)

Enables or disables the High Speed APB (APB2) peripheral clock.

Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Parameters
RCC_APB2Periph,:specifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values:
  • RCC_APB2Periph_TIM1: TIM1 clock
  • RCC_APB2Periph_TIM8: TIM8 clock
  • RCC_APB2Periph_USART1: USART1 clock
  • RCC_APB2Periph_USART6: USART6 clock
  • RCC_APB2Periph_ADC1: ADC1 clock
  • RCC_APB2Periph_ADC2: ADC2 clock
  • RCC_APB2Periph_ADC3: ADC3 clock
  • RCC_APB2Periph_SDIO: SDIO clock
  • RCC_APB2Periph_SPI1: SPI1 clock
  • RCC_APB2Periph_SYSCFG: SYSCFG clock
  • RCC_APB2Periph_TIM9: TIM9 clock
  • RCC_APB2Periph_TIM10: TIM10 clock
  • RCC_APB2Periph_TIM11: TIM11 clock
NewState,:new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values
None
void RCC_APB2PeriphClockLPModeCmd ( uint32_t  RCC_APB2Periph,
FunctionalState  NewState 
)

Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.

Note
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
After wakeup from SLEEP mode, the peripheral clock is enabled again.
By default, all peripheral clocks are enabled during SLEEP mode.
Parameters
RCC_APB2Periph,:specifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values:
  • RCC_APB2Periph_TIM1: TIM1 clock
  • RCC_APB2Periph_TIM8: TIM8 clock
  • RCC_APB2Periph_USART1: USART1 clock
  • RCC_APB2Periph_USART6: USART6 clock
  • RCC_APB2Periph_ADC1: ADC1 clock
  • RCC_APB2Periph_ADC2: ADC2 clock
  • RCC_APB2Periph_ADC3: ADC3 clock
  • RCC_APB2Periph_SDIO: SDIO clock
  • RCC_APB2Periph_SPI1: SPI1 clock
  • RCC_APB2Periph_SYSCFG: SYSCFG clock
  • RCC_APB2Periph_TIM9: TIM9 clock
  • RCC_APB2Periph_TIM10: TIM10 clock
  • RCC_APB2Periph_TIM11: TIM11 clock
NewState,:new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values
None
void RCC_APB2PeriphResetCmd ( uint32_t  RCC_APB2Periph,
FunctionalState  NewState 
)

Forces or releases High Speed APB (APB2) peripheral reset.

Parameters
RCC_APB2Periph,:specifies the APB2 peripheral to reset. This parameter can be any combination of the following values:
  • RCC_APB2Periph_TIM1: TIM1 clock
  • RCC_APB2Periph_TIM8: TIM8 clock
  • RCC_APB2Periph_USART1: USART1 clock
  • RCC_APB2Periph_USART6: USART6 clock
  • RCC_APB2Periph_ADC1: ADC1 clock
  • RCC_APB2Periph_ADC2: ADC2 clock
  • RCC_APB2Periph_ADC3: ADC3 clock
  • RCC_APB2Periph_SDIO: SDIO clock
  • RCC_APB2Periph_SPI1: SPI1 clock
  • RCC_APB2Periph_SYSCFG: SYSCFG clock
  • RCC_APB2Periph_TIM9: TIM9 clock
  • RCC_APB2Periph_TIM10: TIM10 clock
  • RCC_APB2Periph_TIM11: TIM11 clock
NewState,:new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
Return values
None
void RCC_BackupResetCmd ( FunctionalState  NewState)

Forces or releases the Backup domain reset.

Note
This function resets the RTC peripheral (including the backup registers) and the RTC clock source selection in RCC_CSR register.
The BKPSRAM is not affected by this reset.
Parameters
NewState,:new state of the Backup domain reset. This parameter can be: ENABLE or DISABLE.
Return values
None
void RCC_ClearFlag ( void  )

Clears the RCC reset flags. The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.

Parameters
None
Return values
None
void RCC_ClearITPendingBit ( uint8_t  RCC_IT)

Clears the RCC's interrupt pending bits.

Parameters
RCC_IT,:specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:
  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: main PLL ready interrupt
  • RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
  • RCC_IT_CSS: Clock Security System interrupt
Return values
None
void RCC_ClockSecuritySystemCmd ( FunctionalState  NewState)

Enables or disables the Clock Security System.

Note
If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt, CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
Parameters
NewState,:new state of the Clock Security System. This parameter can be: ENABLE or DISABLE.
Return values
None
void RCC_DeInit ( void  )

Resets the RCC clock configuration to the default reset state.

Note
The default reset state of the clock configuration is given below:
  • HSI ON and used as system clock source
  • HSE, PLL and PLLI2S OFF
  • AHB, APB1 and APB2 prescaler set to 1.
  • CSS, MCO1 and MCO2 OFF
  • All interrupts disabled
This function doesn't modify the configuration of the
  • Peripheral clocks
  • LSI, LSE and RTC clocks
Parameters
None
Return values
None
void RCC_GetClocksFreq ( RCC_ClocksTypeDef *  RCC_Clocks)

Returns the frequencies of different on chip clocks; SYSCLK, HCLK, PCLK1 and PCLK2.

Note
The system frequency computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source:
If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) or HSI_VALUE(*) multiplied/divided by the PLL factors.
(*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value 16 MHz) but the real value may vary depending on the variations in voltage and temperature.
(**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value 25 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.
The result of this function could be not correct when using fractional value for HSE crystal.
Parameters
RCC_Clocks,:pointer to a RCC_ClocksTypeDef structure which will hold the clocks frequencies.
Note
This function can be used by the user application to compute the baudrate for the communication peripherals or configure other parameters.
Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function must be called to update the structure's field. Otherwise, any configuration based on this function will be incorrect.
Return values
None
FlagStatus RCC_GetFlagStatus ( uint8_t  RCC_FLAG)

Checks whether the specified RCC flag is set or not.

Parameters
RCC_FLAG,:specifies the flag to check. This parameter can be one of the following values:
  • RCC_FLAG_HSIRDY: HSI oscillator clock ready
  • RCC_FLAG_HSERDY: HSE oscillator clock ready
  • RCC_FLAG_PLLRDY: main PLL clock ready
  • RCC_FLAG_PLLI2SRDY: PLLI2S clock ready
  • RCC_FLAG_LSERDY: LSE oscillator clock ready
  • RCC_FLAG_LSIRDY: LSI oscillator clock ready
  • RCC_FLAG_BORRST: POR/PDR or BOR reset
  • RCC_FLAG_PINRST: Pin reset
  • RCC_FLAG_PORRST: POR/PDR reset
  • RCC_FLAG_SFTRST: Software reset
  • RCC_FLAG_IWDGRST: Independent Watchdog reset
  • RCC_FLAG_WWDGRST: Window Watchdog reset
  • RCC_FLAG_LPWRRST: Low Power reset
Return values
Thenew state of RCC_FLAG (SET or RESET).
ITStatus RCC_GetITStatus ( uint8_t  RCC_IT)

Checks whether the specified RCC interrupt has occurred or not.

Parameters
RCC_IT,:specifies the RCC interrupt source to check. This parameter can be one of the following values:
  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: main PLL ready interrupt
  • RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
  • RCC_IT_CSS: Clock Security System interrupt
Return values
Thenew state of RCC_IT (SET or RESET).
uint8_t RCC_GetSYSCLKSource ( void  )

Returns the clock source used as system clock.

Parameters
None
Return values
Theclock source used as system clock. The returned value can be one of the following:
  • 0x00: HSI used as system clock
  • 0x04: HSE used as system clock
  • 0x08: PLL used as system clock
void RCC_HCLKConfig ( uint32_t  RCC_SYSCLK)

Configures the AHB clock (HCLK).

Note
Depending on the device voltage range, the software has to set correctly these bits to ensure that HCLK not exceed the maximum allowed frequency (for more details refer to section above "CPU, AHB and APB busses clocks configuration functions")
Parameters
RCC_SYSCLK,:defines the AHB clock divider. This clock is derived from the system clock (SYSCLK). This parameter can be one of the following values:
  • RCC_SYSCLK_Div1: AHB clock = SYSCLK
  • RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
  • RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
  • RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
  • RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
  • RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
  • RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
  • RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
  • RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
Return values
None
void RCC_HSEConfig ( uint8_t  RCC_HSE)

Configures the External High Speed oscillator (HSE).

Note
After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application software should wait on HSERDY flag to be set indicating that HSE clock is stable and can be used to clock the PLL and/or system clock.
HSE state can not be changed if it is used directly or through the PLL as system clock. In this case, you have to select another source of the system clock then change the HSE state (ex. disable it).
The HSE is stopped by hardware when entering STOP and STANDBY modes.
This function reset the CSSON bit, so if the Clock security system(CSS) was previously enabled you have to enable it again after calling this function.
Parameters
RCC_HSE,:specifies the new state of the HSE. This parameter can be one of the following values:
  • RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after 6 HSE oscillator clock cycles.
  • RCC_HSE_ON: turn ON the HSE oscillator
  • RCC_HSE_Bypass: HSE oscillator bypassed with external clock
Return values
None
void RCC_HSICmd ( FunctionalState  NewState)

Enables or disables the Internal High Speed oscillator (HSI).

Note
The HSI is stopped by hardware when entering STOP and STANDBY modes. It is used (enabled by hardware) as system clock source after startup from Reset, wakeup from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
HSI can not be stopped if it is used as system clock source. In this case, you have to select another source of the system clock then stop the HSI.
After enabling the HSI, the application software should wait on HSIRDY flag to be set indicating that HSI clock is stable and can be used as system clock source.
Parameters
NewState,:new state of the HSI. This parameter can be: ENABLE or DISABLE.
Note
When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator clock cycles.
Return values
None
void RCC_I2SCLKConfig ( uint32_t  RCC_I2SCLKSource)

Configures the I2S clock source (I2SCLK).

Note
This function must be called before enabling the I2S APB clock.
Parameters
RCC_I2SCLKSource,:specifies the I2S clock source. This parameter can be one of the following values:
  • RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source
  • RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin used as I2S clock source
Return values
None
void RCC_ITConfig ( uint8_t  RCC_IT,
FunctionalState  NewState 
)

Enables or disables the specified RCC interrupts.

Parameters
RCC_IT,:specifies the RCC interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: main PLL ready interrupt
  • RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
NewState,:new state of the specified RCC interrupts. This parameter can be: ENABLE or DISABLE.
Return values
None
void RCC_LSEConfig ( uint8_t  RCC_LSE)

Configures the External Low Speed oscillator (LSE).

Note
As the LSE is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using PWR_BackupAccessCmd(ENABLE) function before to configure the LSE (to be done once after reset).
After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application software should wait on LSERDY flag to be set indicating that LSE clock is stable and can be used to clock the RTC.
Parameters
RCC_LSE,:specifies the new state of the LSE. This parameter can be one of the following values:
  • RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after 6 LSE oscillator clock cycles.
  • RCC_LSE_ON: turn ON the LSE oscillator
  • RCC_LSE_Bypass: LSE oscillator bypassed with external clock
Return values
None
void RCC_LSICmd ( FunctionalState  NewState)

Enables or disables the Internal Low Speed oscillator (LSI).

Note
After enabling the LSI, the application software should wait on LSIRDY flag to be set indicating that LSI clock is stable and can be used to clock the IWDG and/or the RTC.
LSI can not be disabled if the IWDG is running.
Parameters
NewState,:new state of the LSI. This parameter can be: ENABLE or DISABLE.
Note
When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator clock cycles.
Return values
None
void RCC_MCO1Config ( uint32_t  RCC_MCO1Source,
uint32_t  RCC_MCO1Div 
)

Selects the clock source to output on MCO1 pin(PA8).

Note
PA8 should be configured in alternate function mode.
Parameters
RCC_MCO1Source,:specifies the clock source to output. This parameter can be one of the following values:
  • RCC_MCO1Source_HSI: HSI clock selected as MCO1 source
  • RCC_MCO1Source_LSE: LSE clock selected as MCO1 source
  • RCC_MCO1Source_HSE: HSE clock selected as MCO1 source
  • RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source
RCC_MCO1Div,:specifies the MCO1 prescaler. This parameter can be one of the following values:
  • RCC_MCO1Div_1: no division applied to MCO1 clock
  • RCC_MCO1Div_2: division by 2 applied to MCO1 clock
  • RCC_MCO1Div_3: division by 3 applied to MCO1 clock
  • RCC_MCO1Div_4: division by 4 applied to MCO1 clock
  • RCC_MCO1Div_5: division by 5 applied to MCO1 clock
Return values
None
void RCC_MCO2Config ( uint32_t  RCC_MCO2Source,
uint32_t  RCC_MCO2Div 
)

Selects the clock source to output on MCO2 pin(PC9).

Note
PC9 should be configured in alternate function mode.
Parameters
RCC_MCO2Source,:specifies the clock source to output. This parameter can be one of the following values:
  • RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source
  • RCC_MCO2Source_PLLI2SCLK: PLLI2S clock selected as MCO2 source
  • RCC_MCO2Source_HSE: HSE clock selected as MCO2 source
  • RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source
RCC_MCO2Div,:specifies the MCO2 prescaler. This parameter can be one of the following values:
  • RCC_MCO2Div_1: no division applied to MCO2 clock
  • RCC_MCO2Div_2: division by 2 applied to MCO2 clock
  • RCC_MCO2Div_3: division by 3 applied to MCO2 clock
  • RCC_MCO2Div_4: division by 4 applied to MCO2 clock
  • RCC_MCO2Div_5: division by 5 applied to MCO2 clock
Return values
None
void RCC_PCLK1Config ( uint32_t  RCC_HCLK)

Configures the Low Speed APB clock (PCLK1).

Parameters
RCC_HCLK,:defines the APB1 clock divider. This clock is derived from the AHB clock (HCLK). This parameter can be one of the following values:
  • RCC_HCLK_Div1: APB1 clock = HCLK
  • RCC_HCLK_Div2: APB1 clock = HCLK/2
  • RCC_HCLK_Div4: APB1 clock = HCLK/4
  • RCC_HCLK_Div8: APB1 clock = HCLK/8
  • RCC_HCLK_Div16: APB1 clock = HCLK/16
Return values
None
void RCC_PCLK2Config ( uint32_t  RCC_HCLK)

Configures the High Speed APB clock (PCLK2).

Parameters
RCC_HCLK,:defines the APB2 clock divider. This clock is derived from the AHB clock (HCLK). This parameter can be one of the following values:
  • RCC_HCLK_Div1: APB2 clock = HCLK
  • RCC_HCLK_Div2: APB2 clock = HCLK/2
  • RCC_HCLK_Div4: APB2 clock = HCLK/4
  • RCC_HCLK_Div8: APB2 clock = HCLK/8
  • RCC_HCLK_Div16: APB2 clock = HCLK/16
Return values
None
void RCC_PLLCmd ( FunctionalState  NewState)

Enables or disables the main PLL.

Note
After enabling the main PLL, the application software should wait on PLLRDY flag to be set indicating that PLL clock is stable and can be used as system clock source.
The main PLL can not be disabled if it is used as system clock source
The main PLL is disabled by hardware when entering STOP and STANDBY modes.
Parameters
NewState,:new state of the main PLL. This parameter can be: ENABLE or DISABLE.
Return values
None
void RCC_PLLConfig ( uint32_t  RCC_PLLSource,
uint32_t  PLLM,
uint32_t  PLLN,
uint32_t  PLLP,
uint32_t  PLLQ 
)

Configures the main PLL clock source, multiplication and division factors.

Note
This function must be used only when the main PLL is disabled.
Parameters
RCC_PLLSource,:specifies the PLL entry clock source. This parameter can be one of the following values:
  • RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry
  • RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry
Note
This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
Parameters
PLLM,:specifies the division factor for PLL VCO input clock This parameter must be a number between 0 and 63.
Note
You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter.
Parameters
PLLN,:specifies the multiplication factor for PLL VCO output clock This parameter must be a number between 192 and 432.
Note
You have to set the PLLN parameter correctly to ensure that the VCO output frequency is between 192 and 432 MHz.
Parameters
PLLP,:specifies the division factor for main system clock (SYSCLK) This parameter must be a number in the range {2, 4, 6, or 8}.
Note
You have to set the PLLP parameter correctly to not exceed 168 MHz on the System clock frequency.
Parameters
PLLQ,:specifies the division factor for OTG FS, SDIO and RNG clocks This parameter must be a number between 4 and 15.
Note
If the USB OTG FS is used in your application, you have to set the PLLQ parameter correctly to have 48 MHz clock for the USB. However, the SDIO and RNG need a frequency lower than or equal to 48 MHz to work correctly.
Return values
None
void RCC_PLLI2SCmd ( FunctionalState  NewState)

Enables or disables the PLLI2S.

Note
The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
Parameters
NewState,:new state of the PLLI2S. This parameter can be: ENABLE or DISABLE.
Return values
None
void RCC_PLLI2SConfig ( uint32_t  PLLI2SN,
uint32_t  PLLI2SR 
)

Configures the PLLI2S clock multiplication and division factors.

Note
This function must be used only when the PLLI2S is disabled.
PLLI2S clock source is common with the main PLL (configured in RCC_PLLConfig function )
Parameters
PLLI2SN,:specifies the multiplication factor for PLLI2S VCO output clock This parameter must be a number between 192 and 432.
Note
You have to set the PLLI2SN parameter correctly to ensure that the VCO output frequency is between 192 and 432 MHz.
Parameters
PLLI2SR,:specifies the division factor for I2S clock This parameter must be a number between 2 and 7.
Note
You have to set the PLLI2SR parameter correctly to not exceed 192 MHz on the I2S clock frequency.
Return values
None
void RCC_RTCCLKCmd ( FunctionalState  NewState)

Enables or disables the RTC clock.

Note
This function must be used only after the RTC clock source was selected using the RCC_RTCCLKConfig function.
Parameters
NewState,:new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
Return values
None
void RCC_RTCCLKConfig ( uint32_t  RCC_RTCCLKSource)

Configures the RTC clock (RTCCLK).

Note
As the RTC clock configuration bits are in the Backup domain and write access is denied to this domain after reset, you have to enable write access using PWR_BackupAccessCmd(ENABLE) function before to configure the RTC clock source (to be done once after reset).
Once the RTC clock is configured it can't be changed unless the Backup domain is reset using RCC_BackupResetCmd() function, or by a Power On Reset (POR).
Parameters
RCC_RTCCLKSource,:specifies the RTC clock source. This parameter can be one of the following values:
  • RCC_RTCCLKSource_LSE: LSE selected as RTC clock
  • RCC_RTCCLKSource_LSI: LSI selected as RTC clock
  • RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected as RTC clock, where x:[2,31]
Note
If the LSE or LSI is used as RTC clock source, the RTC continues to work in STOP and STANDBY modes, and can be used as wakeup source. However, when the HSE clock is used as RTC clock source, the RTC cannot be used in STOP and STANDBY modes.
The maximum input clock frequency for RTC is 1MHz (when using HSE as RTC clock source).
Return values
None
void RCC_SYSCLKConfig ( uint32_t  RCC_SYSCLKSource)

Configures the system clock (SYSCLK).

Note
The HSI is used (enabled by hardware) as system clock source after startup from Reset, wake-up from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready. You can use RCC_GetSYSCLKSource() function to know which clock is currently used as system clock source.
Parameters
RCC_SYSCLKSource,:specifies the clock source used as system clock. This parameter can be one of the following values:
  • RCC_SYSCLKSource_HSI: HSI selected as system clock source
  • RCC_SYSCLKSource_HSE: HSE selected as system clock source
  • RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
Return values
None
ErrorStatus RCC_WaitForHSEStartUp ( void  )

Waits for HSE start-up.

Note
This functions waits on HSERDY flag to be set and return SUCCESS if this flag is set, otherwise returns ERROR if the timeout is reached and this flag is not set. The timeout value is defined by the constant HSE_STARTUP_TIMEOUT in stm32f4xx.h file. You can tailor it depending on the HSE crystal used in your application.
Parameters
None
Return values
AnErrorStatus enumeration value:
  • SUCCESS: HSE oscillator is stable and ready to use
  • ERROR: HSE oscillator not yet ready