System, AHB and APB busses clocks configuration functions.
More...
System, AHB and APB busses clocks configuration functions.
===============================================================================
##### System, AHB, APB1 and APB2 busses clocks configuration functions #####
===============================================================================
[..] This section provide functions allowing to configure the System, AHB, APB1 and
APB2 busses clocks.
(#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
HSE and PLL.
The AHB clock (HCLK) is derived from System clock through configurable prescaler
and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA and GPIO).
APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through
configurable prescalers and used to clock the peripherals mapped on these busses.
You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.
-@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
(+@) The FLASH program/erase clock which is always HSI 8MHz clock.
(+@) The USB 48 MHz clock which is derived from the PLL VCO clock.
(+@) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE.
(+@) The I2C clock which can be derived as well from HSI 8MHz clock.
(+@) The CEC clock which can be derived from HSI 8MHz or LSE.
(+@) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC (HSE
divided by a programmable prescaler).
The System clock (SYSCLK) frequency must be higher or equal to the RTC
clock frequency.
(+@) IWDG clock which is always the LSI clock.
(#) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 72 MHz.
Depending on the maximum frequency, the FLASH wait states (WS) should be
adapted accordingly:
+---------------------------------+
| Wait states | HCLK clock |
| (Latency) | frequency (MHz) |
|-------------- |-----------------|
|0WS(1CPU cycle)| 0 < HCLK <= 24 |
|---------------|-----------------|
|1WS(2CPU cycle)|24 < HCLK <=48 |
|---------------|-----------------|
|2WS(3CPU cycle)|48 < HCLK <= 72 |
+---------------------------------+
(#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and
prefetch is disabled.
[..] It is recommended to use the following software sequences to tune the number
of wait states needed to access the Flash memory with the CPU frequency (HCLK).
(+) Increasing the CPU frequency
(++) Program the Flash Prefetch buffer, using "FLASH_PrefetchBufferCmd(ENABLE)"
function
(++) Check that Flash Prefetch buffer activation is taken into account by
reading FLASH_ACR using the FLASH_GetPrefetchBufferStatus() function
(++) Program Flash WS to 1 or 2, using "FLASH_SetLatency()" function
(++) Check that the new number of WS is taken into account by reading FLASH_ACR
(++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
(++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
(++) Check that the new CPU clock source is taken into account by reading
the clock source status, using "RCC_GetSYSCLKSource()" function
(+) Decreasing the CPU frequency
(++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
(++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
(++) Check that the new CPU clock source is taken into account by reading
the clock source status, using "RCC_GetSYSCLKSource()" function
(++) Program the new number of WS, using "FLASH_SetLatency()" function
(++) Check that the new number of WS is taken into account by reading FLASH_ACR
(++) Disable the Flash Prefetch buffer using "FLASH_PrefetchBufferCmd(DISABLE)"
function
(++) Check that Flash Prefetch buffer deactivation is taken into account by reading FLASH_ACR
using the FLASH_GetPrefetchBufferStatus() function.
| void RCC_ADCCLKConfig |
( |
uint32_t |
RCC_PCLK2 | ) |
|
Configures the ADC clock (ADCCLK).
- Parameters
-
| RCC_PCLK2,: | defines the ADC clock divider. This clock is derived from the APB2 clock (PCLK2). This parameter can be one of the following values:
- RCC_PCLK2_Div2: ADC clock = PCLK2/2
- RCC_PCLK2_Div4: ADC clock = PCLK2/4
- RCC_PCLK2_Div6: ADC clock = PCLK2/6
- RCC_PCLK2_Div8: ADC clock = PCLK2/8
|
- Return values
-
| void RCC_CECCLKConfig |
( |
uint32_t |
RCC_CECCLK | ) |
|
Configures the CEC clock (CECCLK).
- Parameters
-
| RCC_CECCLK,: | defines the CEC clock source. This clock is derived from the HSI or LSE clock. This parameter can be one of the following values:
- RCC_CECCLK_HSI_Div244: CEC clock = HSI/244 (32768Hz)
- RCC_CECCLK_LSE: CEC clock = LSE
|
- Return values
-
Returns the frequencies of the System, AHB, APB2 and APB1 busses clocks.
- Note
- The frequency returned by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the source selected by RCC_SYSCLKConfig():
-
If SYSCLK source is HSI, function returns constant HSI_VALUE(*)
-
If SYSCLK source is HSE, function returns constant HSE_VALUE(**)
-
If SYSCLK source is PLL, function returns constant HSE_VALUE(**) or HSI_VALUE(*) multiplied by the PLL factors.
-
(*) HSI_VALUE is a constant defined in stm32f37x.h file (default value 8 MHz) but the real value may vary depending on the variations in voltage and temperature, refer to RCC_AdjustHSICalibrationValue().
-
(**) HSE_VALUE is a constant defined in stm32f37x.h file (default value 8 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may return wrong result.
-
The result of this function could be not correct when using fractional value for HSE crystal.
- Parameters
-
| RCC_Clocks,: | pointer to a RCC_ClocksTypeDef structure which will hold the clocks frequencies. |
- Note
- This function can be used by the user application to compute the baudrate for the communication peripherals or configure other parameters.
-
Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function must be called to update the structure's field. Otherwise, any configuration based on this function will be incorrect.
- Return values
-
| uint8_t RCC_GetSYSCLKSource |
( |
void |
| ) |
|
Returns the clock source used as system clock.
- Parameters
-
- Return values
-
| The | clock source used as system clock. The returned value can be one of the following values:
- 0x00: HSI used as system clock
- 0x04: HSE used as system clock
- 0x08: PLL used as system clock
|
| void RCC_HCLKConfig |
( |
uint32_t |
RCC_SYSCLK | ) |
|
Configures the AHB clock (HCLK).
- Parameters
-
| RCC_SYSCLK,: | defines the AHB clock divider. This clock is derived from the system clock (SYSCLK). This parameter can be one of the following values:
- RCC_SYSCLK_Div1: AHB clock = SYSCLK
- RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
- RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
- RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
- RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
- RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
- RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
- RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
- RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
|
- Return values
-
| void RCC_I2CCLKConfig |
( |
uint32_t |
RCC_I2CCLK | ) |
|
Configures the I2C clock (I2CCLK).
- Parameters
-
| RCC_I2CCLK,: | defines the I2C clock source. This clock is derived from the HSI or System clock. This parameter can be one of the following values:
- RCC_I2CxCLK_HSI: I2Cx clock = HSI
- RCC_I2CxCLK_SYSCLK: I2Cx clock = System Clock
|
- Note
- x can be 1 or 2
- Return values
-
| void RCC_PCLK1Config |
( |
uint32_t |
RCC_HCLK | ) |
|
Configures the Low Speed APB clock (PCLK1).
- Parameters
-
| RCC_HCLK,: | defines the APB1 clock divider. This clock is derived from the AHB clock (HCLK). This parameter can be one of the following values:
- RCC_HCLK_Div1: APB1 clock = HCLK
- RCC_HCLK_Div2: APB1 clock = HCLK/2
- RCC_HCLK_Div4: APB1 clock = HCLK/4
- RCC_HCLK_Div8: APB1 clock = HCLK/8
- RCC_HCLK_Div16: APB1 clock = HCLK/16
|
- Return values
-
| void RCC_PCLK2Config |
( |
uint32_t |
RCC_HCLK | ) |
|
Configures the High Speed APB clock (PCLK2).
- Parameters
-
| RCC_HCLK,: | defines the APB2 clock divider. This clock is derived from the AHB clock (HCLK). This parameter can be one of the following values:
- RCC_HCLK_Div1: APB2 clock = HCLK
- RCC_HCLK_Div2: APB2 clock = HCLK/2
- RCC_HCLK_Div4: APB2 clock = HCLK/4
- RCC_HCLK_Div8: APB2 clock = HCLK/8
- RCC_HCLK_Div16: APB2 clock = HCLK/16
|
- Return values
-
| void RCC_SDADCCLKConfig |
( |
uint32_t |
RCC_SDADCCLK | ) |
|
Configures the SDADC clock (SDADCCLK).
- Parameters
-
| RCC_PCLK2,: | defines the ADC clock divider. This clock is derived from the system clock (SYSCLK). This parameter can be one of the following values:
- RCC_SDADCCLK_SYSCLK_Div2: SDADC clock = SYSCLK/2
- RCC_SDADCCLK_SYSCLK_Div4: SDADC clock = SYSCLK/4
- RCC_SDADCCLK_SYSCLK_Div6: SDADC clock = SYSCLK/6
- RCC_SDADCCLK_SYSCLK_Div8: SDADC clock = SYSCLK/8
- RCC_SDADCCLK_SYSCLK_Div10: SDADC clock = SYSCLK/10
- RCC_SDADCCLK_SYSCLK_Div12: SDADC clock = SYSCLK/12
- RCC_SDADCCLK_SYSCLK_Div14: SDADC clock = SYSCLK/14
- RCC_SDADCCLK_SYSCLK_Div16: SDADC clock = SYSCLK/16
- RCC_SDADCCLK_SYSCLK_Div20: SDADC clock = SYSCLK/20
- RCC_SDADCCLK_SYSCLK_Div24: SDADC clock = SYSCLK/24
- RCC_SDADCCLK_SYSCLK_Div28: SDADC clock = SYSCLK/28
- RCC_SDADCCLK_SYSCLK_Div32: SDADC clock = SYSCLK/32
- RCC_SDADCCLK_SYSCLK_Div36: SDADC clock = SYSCLK/36
- RCC_SDADCCLK_SYSCLK_Div40: SDADC clock = SYSCLK/40
- RCC_SDADCCLK_SYSCLK_Div44: SDADC clock = SYSCLK/44
- RCC_SDADCCLK_SYSCLK_Div48: SDADC clock = SYSCLK/48
|
- Return values
-
| void RCC_SYSCLKConfig |
( |
uint32_t |
RCC_SYSCLKSource | ) |
|
Configures the system clock (SYSCLK).
- Note
- The HSI is used (enabled by hardware) as system clock source after startup from Reset, wake-up from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
-
A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready. You can use RCC_GetSYSCLKSource() function to know which clock is currently used as system clock source.
- Parameters
-
| RCC_SYSCLKSource,: | specifies the clock source used as system clock source This parameter can be one of the following values:
- RCC_SYSCLKSource_HSI: HSI selected as system clock source
- RCC_SYSCLKSource_HSE: HSE selected as system clock source
- RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
|
- Return values
-
| void RCC_USARTCLKConfig |
( |
uint32_t |
RCC_USARTCLK | ) |
|
Configures the USART clock (USARTCLK).
- Parameters
-
| RCC_USARTCLK,: | defines the USART clock source. This clock is derived from the HSI or System clock. This parameter can be one of the following values:
- RCC_USARTxCLK_PCLK: USART clock = APB Clock (PCLK)
- RCC_USARTxCLK_SYSCLK: USART clock = System Clock
- RCC_USARTxCLK_LSE: USART clock = LSE Clock
- RCC_USARTxCLK_HSI: USART clock = HSI Clock
|
- Note
- x can be 1, 2 or 3
- Return values
-
| void RCC_USBCLKConfig |
( |
uint32_t |
RCC_USBCLKSource | ) |
|
Configures the USB clock (USBCLK).
- Parameters
-
| RCC_USBCLKSource,: | specifies the USB clock source. This clock is derived from the PLL output. This parameter can be one of the following values:
- RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB clock source
- RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
|
- Return values
-
1.8.3.1