STM32F37 Standard Peripheral bibliotheek  1.0
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stm32f37x_spi.h
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1 
29 /* Define to prevent recursive inclusion -------------------------------------*/
30 #ifndef __STM32F37X_SPI_H
31 #define __STM32F37X_SPI_H
32 
33 #ifdef __cplusplus
34  extern "C" {
35 #endif
36 
37 /* Includes ------------------------------------------------------------------*/
38 #include "stm32f37x.h"
39 
48 /* Exported types ------------------------------------------------------------*/
49 
54 typedef struct
55 {
56  uint16_t SPI_Direction;
59  uint16_t SPI_Mode;
62  uint16_t SPI_DataSize;
65  uint16_t SPI_CPOL;
68  uint16_t SPI_CPHA;
71  uint16_t SPI_NSS;
75  uint16_t SPI_BaudRatePrescaler;
81  uint16_t SPI_FirstBit;
84  uint16_t SPI_CRCPolynomial;
85 }SPI_InitTypeDef;
86 
87 
92 typedef struct
93 {
94  uint16_t I2S_Mode;
97  uint16_t I2S_Standard;
100  uint16_t I2S_DataFormat;
103  uint16_t I2S_MCLKOutput;
106  uint32_t I2S_AudioFreq;
109  uint16_t I2S_CPOL;
111 }I2S_InitTypeDef;
112 
113 /* Exported constants --------------------------------------------------------*/
114 
119 #define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
120  ((PERIPH) == SPI2) || \
121  ((PERIPH) == SPI3))
122 
127 #define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
128 #define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
129 #define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
130 #define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
131 #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
132  ((MODE) == SPI_Direction_2Lines_RxOnly) || \
133  ((MODE) == SPI_Direction_1Line_Rx) || \
134  ((MODE) == SPI_Direction_1Line_Tx))
135 
143 #define SPI_Mode_Master ((uint16_t)0x0104)
144 #define SPI_Mode_Slave ((uint16_t)0x0000)
145 #define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
146  ((MODE) == SPI_Mode_Slave))
147 
155 #define SPI_DataSize_4b ((uint16_t)0x0300)
156 #define SPI_DataSize_5b ((uint16_t)0x0400)
157 #define SPI_DataSize_6b ((uint16_t)0x0500)
158 #define SPI_DataSize_7b ((uint16_t)0x0600)
159 #define SPI_DataSize_8b ((uint16_t)0x0700)
160 #define SPI_DataSize_9b ((uint16_t)0x0800)
161 #define SPI_DataSize_10b ((uint16_t)0x0900)
162 #define SPI_DataSize_11b ((uint16_t)0x0A00)
163 #define SPI_DataSize_12b ((uint16_t)0x0B00)
164 #define SPI_DataSize_13b ((uint16_t)0x0C00)
165 #define SPI_DataSize_14b ((uint16_t)0x0D00)
166 #define SPI_DataSize_15b ((uint16_t)0x0E00)
167 #define SPI_DataSize_16b ((uint16_t)0x0F00)
168 #define IS_SPI_DATA_SIZE(SIZE) (((SIZE) == SPI_DataSize_4b) || \
169  ((SIZE) == SPI_DataSize_5b) || \
170  ((SIZE) == SPI_DataSize_6b) || \
171  ((SIZE) == SPI_DataSize_7b) || \
172  ((SIZE) == SPI_DataSize_8b) || \
173  ((SIZE) == SPI_DataSize_9b) || \
174  ((SIZE) == SPI_DataSize_10b) || \
175  ((SIZE) == SPI_DataSize_11b) || \
176  ((SIZE) == SPI_DataSize_12b) || \
177  ((SIZE) == SPI_DataSize_13b) || \
178  ((SIZE) == SPI_DataSize_14b) || \
179  ((SIZE) == SPI_DataSize_15b) || \
180  ((SIZE) == SPI_DataSize_16b))
181 
189 #define SPI_CRCLength_8b ((uint16_t)0x0000)
190 #define SPI_CRCLength_16b SPI_CR1_CRCL
191 #define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRCLength_8b) || \
192  ((LENGTH) == SPI_CRCLength_16b))
193 
201 #define SPI_CPOL_Low ((uint16_t)0x0000)
202 #define SPI_CPOL_High SPI_CR1_CPOL
203 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
204  ((CPOL) == SPI_CPOL_High))
205 
213 #define SPI_CPHA_1Edge ((uint16_t)0x0000)
214 #define SPI_CPHA_2Edge SPI_CR1_CPHA
215 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
216  ((CPHA) == SPI_CPHA_2Edge))
217 
225 #define SPI_NSS_Soft SPI_CR1_SSM
226 #define SPI_NSS_Hard ((uint16_t)0x0000)
227 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
228  ((NSS) == SPI_NSS_Hard))
229 
237 #define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
238 #define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
239 #define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
240 #define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
241 #define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
242 #define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
243 #define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
244 #define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
245 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
246  ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
247  ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
248  ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
249  ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
250  ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
251  ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
252  ((PRESCALER) == SPI_BaudRatePrescaler_256))
253 
261 #define SPI_FirstBit_MSB ((uint16_t)0x0000)
262 #define SPI_FirstBit_LSB SPI_CR1_LSBFIRST
263 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
264  ((BIT) == SPI_FirstBit_LSB))
265 
273 #define I2S_Mode_SlaveTx ((uint16_t)0x0000)
274 #define I2S_Mode_SlaveRx ((uint16_t)0x0100)
275 #define I2S_Mode_MasterTx ((uint16_t)0x0200)
276 #define I2S_Mode_MasterRx ((uint16_t)0x0300)
277 #define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
278  ((MODE) == I2S_Mode_SlaveRx) || \
279  ((MODE) == I2S_Mode_MasterTx)|| \
280  ((MODE) == I2S_Mode_MasterRx))
281 
289 #define I2S_Standard_Phillips ((uint16_t)0x0000)
290 #define I2S_Standard_MSB ((uint16_t)0x0010)
291 #define I2S_Standard_LSB ((uint16_t)0x0020)
292 #define I2S_Standard_PCMShort ((uint16_t)0x0030)
293 #define I2S_Standard_PCMLong ((uint16_t)0x00B0)
294 #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
295  ((STANDARD) == I2S_Standard_MSB) || \
296  ((STANDARD) == I2S_Standard_LSB) || \
297  ((STANDARD) == I2S_Standard_PCMShort) || \
298  ((STANDARD) == I2S_Standard_PCMLong))
299 
307 #define I2S_DataFormat_16b ((uint16_t)0x0000)
308 #define I2S_DataFormat_16bextended ((uint16_t)0x0001)
309 #define I2S_DataFormat_24b ((uint16_t)0x0003)
310 #define I2S_DataFormat_32b ((uint16_t)0x0005)
311 #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
312  ((FORMAT) == I2S_DataFormat_16bextended) || \
313  ((FORMAT) == I2S_DataFormat_24b) || \
314  ((FORMAT) == I2S_DataFormat_32b))
315 
323 #define I2S_MCLKOutput_Enable SPI_I2SPR_MCKOE
324 #define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
325 #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
326  ((OUTPUT) == I2S_MCLKOutput_Disable))
327 
335 #define I2S_AudioFreq_192k ((uint32_t)192000)
336 #define I2S_AudioFreq_96k ((uint32_t)96000)
337 #define I2S_AudioFreq_48k ((uint32_t)48000)
338 #define I2S_AudioFreq_44k ((uint32_t)44100)
339 #define I2S_AudioFreq_32k ((uint32_t)32000)
340 #define I2S_AudioFreq_22k ((uint32_t)22050)
341 #define I2S_AudioFreq_16k ((uint32_t)16000)
342 #define I2S_AudioFreq_11k ((uint32_t)11025)
343 #define I2S_AudioFreq_8k ((uint32_t)8000)
344 #define I2S_AudioFreq_Default ((uint32_t)2)
345 
346 #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
347  ((FREQ) <= I2S_AudioFreq_192k)) || \
348  ((FREQ) == I2S_AudioFreq_Default))
349 
357 #define I2S_CPOL_Low ((uint16_t)0x0000)
358 #define I2S_CPOL_High SPI_I2SCFGR_CKPOL
359 #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
360  ((CPOL) == I2S_CPOL_High))
361 
369 #define SPI_RxFIFOThreshold_HF ((uint16_t)0x0000)
370 #define SPI_RxFIFOThreshold_QF SPI_CR2_FRXTH
371 #define IS_SPI_RX_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_RxFIFOThreshold_HF) || \
372  ((THRESHOLD) == SPI_RxFIFOThreshold_QF))
373 
381 #define SPI_I2S_DMAReq_Tx SPI_CR2_TXDMAEN
382 #define SPI_I2S_DMAReq_Rx SPI_CR2_RXDMAEN
383 #define IS_SPI_I2S_DMA_REQ(REQ) ((((REQ) & (uint16_t)0xFFFC) == 0x00) && ((REQ) != 0x00))
384 
392 #define SPI_LastDMATransfer_TxEvenRxEven ((uint16_t)0x0000)
393 #define SPI_LastDMATransfer_TxOddRxEven ((uint16_t)0x4000)
394 #define SPI_LastDMATransfer_TxEvenRxOdd ((uint16_t)0x2000)
395 #define SPI_LastDMATransfer_TxOddRxOdd ((uint16_t)0x6000)
396 #define IS_SPI_LAST_DMA_TRANSFER(TRANSFER) (((TRANSFER) == SPI_LastDMATransfer_TxEvenRxEven) || \
397  ((TRANSFER) == SPI_LastDMATransfer_TxOddRxEven) || \
398  ((TRANSFER) == SPI_LastDMATransfer_TxEvenRxOdd) || \
399  ((TRANSFER) == SPI_LastDMATransfer_TxOddRxOdd))
400 
407 #define SPI_NSSInternalSoft_Set SPI_CR1_SSI
408 #define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
409 #define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
410  ((INTERNAL) == SPI_NSSInternalSoft_Reset))
411 
419 #define SPI_CRC_Tx ((uint8_t)0x00)
420 #define SPI_CRC_Rx ((uint8_t)0x01)
421 #define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
422 
430 #define SPI_Direction_Rx ((uint16_t)0xBFFF)
431 #define SPI_Direction_Tx ((uint16_t)0x4000)
432 #define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
433  ((DIRECTION) == SPI_Direction_Tx))
434 
442 #define SPI_I2S_IT_TXE ((uint8_t)0x71)
443 #define SPI_I2S_IT_RXNE ((uint8_t)0x60)
444 #define SPI_I2S_IT_ERR ((uint8_t)0x50)
445 
446 #define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
447  ((IT) == SPI_I2S_IT_RXNE) || \
448  ((IT) == SPI_I2S_IT_ERR))
449 
450 #define I2S_IT_UDR ((uint8_t)0x53)
451 #define SPI_IT_MODF ((uint8_t)0x55)
452 #define SPI_I2S_IT_OVR ((uint8_t)0x56)
453 #define SPI_I2S_IT_FRE ((uint8_t)0x58)
454 
455 #define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
456  ((IT) == SPI_I2S_IT_OVR) || ((IT) == SPI_IT_MODF) || \
457  ((IT) == SPI_I2S_IT_FRE)|| ((IT) == I2S_IT_UDR))
458 
467 #define SPI_TransmissionFIFOStatus_Empty ((uint16_t)0x0000)
468 #define SPI_TransmissionFIFOStatus_1QuarterFull ((uint16_t)0x0800)
469 #define SPI_TransmissionFIFOStatus_HalfFull ((uint16_t)0x1000)
470 #define SPI_TransmissionFIFOStatus_Full ((uint16_t)0x1800)
471 
479 #define SPI_ReceptionFIFOStatus_Empty ((uint16_t)0x0000)
480 #define SPI_ReceptionFIFOStatus_1QuarterFull ((uint16_t)0x0200)
481 #define SPI_ReceptionFIFOStatus_HalfFull ((uint16_t)0x0400)
482 #define SPI_ReceptionFIFOStatus_Full ((uint16_t)0x0600)
483 
493 #define SPI_I2S_FLAG_RXNE SPI_SR_RXNE
494 #define SPI_I2S_FLAG_TXE SPI_SR_TXE
495 #define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
496 #define I2S_FLAG_UDR SPI_SR_UDR
497 #define SPI_FLAG_CRCERR SPI_SR_CRCERR
498 #define SPI_FLAG_MODF SPI_SR_MODF
499 #define SPI_I2S_FLAG_OVR SPI_SR_OVR
500 #define SPI_I2S_FLAG_BSY SPI_SR_BSY
501 #define SPI_I2S_FLAG_FRE SPI_SR_FRE
502 
503 
504 
505 #define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
506 #define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
507  ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
508  ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
509  ((FLAG) == SPI_I2S_FLAG_FRE)|| ((FLAG) == I2S_FLAG_CHSIDE)|| \
510  ((FLAG) == I2S_FLAG_UDR))
511 
519 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
520 
528 /* Exported macro ------------------------------------------------------------*/
529 /* Exported functions ------------------------------------------------------- */
530 
531 /* Initialization and Configuration functions *********************************/
532 void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
533 void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
534 void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
535 void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
536 void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
537 void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
538 void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
539 void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
540 void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
541 void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
542 void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold);
543 void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
544 void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
545 void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
546 
547 /* Data transfers functions ***************************************************/
548 void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data);
549 void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data);
550 uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx);
551 uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx);
552 
553 /* Hardware CRC Calculation functions *****************************************/
554 void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength);
555 void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
556 void SPI_TransmitCRC(SPI_TypeDef* SPIx);
557 uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
558 uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
559 
560 /* DMA transfers management functions *****************************************/
561 void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
562 void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer);
563 
564 /* Interrupts and flags management functions **********************************/
565 void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
566 uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx);
567 uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx);
568 FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
569 void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
570 ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
571 
572 #ifdef __cplusplus
573 }
574 #endif
575 
576 #endif /*__STM32F37X_SPI_H */
577 
586 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/