STM32F1 Standard Peripheral bibliotheek  1.0
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stm32f10x_i2c.h
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1 
22 /* Define to prevent recursive inclusion -------------------------------------*/
23 #ifndef __STM32F10x_I2C_H
24 #define __STM32F10x_I2C_H
25 
26 #ifdef __cplusplus
27  extern "C" {
28 #endif
29 
30 /* Includes ------------------------------------------------------------------*/
31 #include "stm32f10x.h"
32 
49 typedef struct
50 {
51  uint32_t I2C_ClockSpeed;
54  uint16_t I2C_Mode;
57  uint16_t I2C_DutyCycle;
60  uint16_t I2C_OwnAddress1;
63  uint16_t I2C_Ack;
66  uint16_t I2C_AcknowledgedAddress;
68 }I2C_InitTypeDef;
69 
79 #define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
80  ((PERIPH) == I2C2))
81 
85 #define I2C_Mode_I2C ((uint16_t)0x0000)
86 #define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
87 #define I2C_Mode_SMBusHost ((uint16_t)0x000A)
88 #define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
89  ((MODE) == I2C_Mode_SMBusDevice) || \
90  ((MODE) == I2C_Mode_SMBusHost))
91 
99 #define I2C_DutyCycle_16_9 ((uint16_t)0x4000)
100 #define I2C_DutyCycle_2 ((uint16_t)0xBFFF)
101 #define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
102  ((CYCLE) == I2C_DutyCycle_2))
103 
111 #define I2C_Ack_Enable ((uint16_t)0x0400)
112 #define I2C_Ack_Disable ((uint16_t)0x0000)
113 #define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
114  ((STATE) == I2C_Ack_Disable))
115 
123 #define I2C_Direction_Transmitter ((uint8_t)0x00)
124 #define I2C_Direction_Receiver ((uint8_t)0x01)
125 #define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
126  ((DIRECTION) == I2C_Direction_Receiver))
127 
135 #define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
136 #define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
137 #define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
138  ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
139 
147 #define I2C_Register_CR1 ((uint8_t)0x00)
148 #define I2C_Register_CR2 ((uint8_t)0x04)
149 #define I2C_Register_OAR1 ((uint8_t)0x08)
150 #define I2C_Register_OAR2 ((uint8_t)0x0C)
151 #define I2C_Register_DR ((uint8_t)0x10)
152 #define I2C_Register_SR1 ((uint8_t)0x14)
153 #define I2C_Register_SR2 ((uint8_t)0x18)
154 #define I2C_Register_CCR ((uint8_t)0x1C)
155 #define I2C_Register_TRISE ((uint8_t)0x20)
156 #define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
157  ((REGISTER) == I2C_Register_CR2) || \
158  ((REGISTER) == I2C_Register_OAR1) || \
159  ((REGISTER) == I2C_Register_OAR2) || \
160  ((REGISTER) == I2C_Register_DR) || \
161  ((REGISTER) == I2C_Register_SR1) || \
162  ((REGISTER) == I2C_Register_SR2) || \
163  ((REGISTER) == I2C_Register_CCR) || \
164  ((REGISTER) == I2C_Register_TRISE))
165 
173 #define I2C_SMBusAlert_Low ((uint16_t)0x2000)
174 #define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
175 #define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
176  ((ALERT) == I2C_SMBusAlert_High))
177 
185 #define I2C_PECPosition_Next ((uint16_t)0x0800)
186 #define I2C_PECPosition_Current ((uint16_t)0xF7FF)
187 #define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
188  ((POSITION) == I2C_PECPosition_Current))
189 
197 #define I2C_IT_BUF ((uint16_t)0x0400)
198 #define I2C_IT_EVT ((uint16_t)0x0200)
199 #define I2C_IT_ERR ((uint16_t)0x0100)
200 #define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
201 
209 #define I2C_IT_SMBALERT ((uint32_t)0x01008000)
210 #define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
211 #define I2C_IT_PECERR ((uint32_t)0x01001000)
212 #define I2C_IT_OVR ((uint32_t)0x01000800)
213 #define I2C_IT_AF ((uint32_t)0x01000400)
214 #define I2C_IT_ARLO ((uint32_t)0x01000200)
215 #define I2C_IT_BERR ((uint32_t)0x01000100)
216 #define I2C_IT_TXE ((uint32_t)0x06000080)
217 #define I2C_IT_RXNE ((uint32_t)0x06000040)
218 #define I2C_IT_STOPF ((uint32_t)0x02000010)
219 #define I2C_IT_ADD10 ((uint32_t)0x02000008)
220 #define I2C_IT_BTF ((uint32_t)0x02000004)
221 #define I2C_IT_ADDR ((uint32_t)0x02000002)
222 #define I2C_IT_SB ((uint32_t)0x02000001)
223 
224 #define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
225 
226 #define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
227  ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
228  ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
229  ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
230  ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
231  ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
232  ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
233 
245 #define I2C_FLAG_DUALF ((uint32_t)0x00800000)
246 #define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
247 #define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
248 #define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
249 #define I2C_FLAG_TRA ((uint32_t)0x00040000)
250 #define I2C_FLAG_BUSY ((uint32_t)0x00020000)
251 #define I2C_FLAG_MSL ((uint32_t)0x00010000)
252 
257 #define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
258 #define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
259 #define I2C_FLAG_PECERR ((uint32_t)0x10001000)
260 #define I2C_FLAG_OVR ((uint32_t)0x10000800)
261 #define I2C_FLAG_AF ((uint32_t)0x10000400)
262 #define I2C_FLAG_ARLO ((uint32_t)0x10000200)
263 #define I2C_FLAG_BERR ((uint32_t)0x10000100)
264 #define I2C_FLAG_TXE ((uint32_t)0x10000080)
265 #define I2C_FLAG_RXNE ((uint32_t)0x10000040)
266 #define I2C_FLAG_STOPF ((uint32_t)0x10000010)
267 #define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
268 #define I2C_FLAG_BTF ((uint32_t)0x10000004)
269 #define I2C_FLAG_ADDR ((uint32_t)0x10000002)
270 #define I2C_FLAG_SB ((uint32_t)0x10000001)
271 
272 #define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
273 
274 #define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
275  ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
276  ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
277  ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
278  ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
279  ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
280  ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
281  ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
282  ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
283  ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
284  ((FLAG) == I2C_FLAG_SB))
285 
293 /*========================================
294 
295  I2C Master Events (Events grouped in order of communication)
296  ==========================================*/
305 /* --EV5 */
306 #define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
307 
333 /* --EV6 */
334 #define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
335 #define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
336 /* --EV9 */
337 #define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
338 
368 /* Master RECEIVER mode -----------------------------*/
369 /* --EV7 */
370 #define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
371 
372 /* Master TRANSMITTER mode --------------------------*/
373 /* --EV8 */
374 #define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
375 /* --EV8_2 */
376 #define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
377 
378 
379 /*========================================
380 
381  I2C Slave Events (Events grouped in order of communication)
382  ==========================================*/
383 
409 /* --EV1 (all the events below are variants of EV1) */
410 /* 1) Case of One Single Address managed by the slave */
411 #define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
412 #define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
413 
414 /* 2) Case of Dual address managed by the slave */
415 #define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
416 #define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
417 
418 /* 3) Case of General Call enabled for the slave */
419 #define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
420 
448 /* Slave RECEIVER mode --------------------------*/
449 /* --EV2 */
450 #define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
451 /* --EV4 */
452 #define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
453 
454 /* Slave TRANSMITTER mode -----------------------*/
455 /* --EV3 */
456 #define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
457 #define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
458 /* --EV3_2 */
459 #define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
460 
461 /*=========================== End of Events Description ==========================================*/
462 
463 #define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
464  ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
465  ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
466  ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
467  ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
468  ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
469  ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
470  ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
471  ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
472  ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
473  ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
474  ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
475  ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
476  ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
477  ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
478  ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
479  ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
480  ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
481  ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
482  ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
483 
491 #define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
492 
500 #define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
501 
521 void I2C_DeInit(I2C_TypeDef* I2Cx);
522 void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
523 void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
524 void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
525 void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
526 void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
527 void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
528 void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
529 void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
530 void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
531 void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
532 void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
533 void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
534 void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
535 uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
536 void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
537 uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
538 void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
539 void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
540 void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
541 void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
542 void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
543 uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
544 void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
545 void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
546 void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
547 
631 ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
637 uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
643 FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
649 void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
650 ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
651 void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
652 
653 #ifdef __cplusplus
654 }
655 #endif
656 
657 #endif /*__STM32F10x_I2C_H */
658 
670 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/