23 #ifndef __STM32F10x_FSMC_H
24 #define __STM32F10x_FSMC_H
31 #include "stm32f10x.h"
51 uint32_t FSMC_AddressSetupTime;
56 uint32_t FSMC_AddressHoldTime;
61 uint32_t FSMC_DataSetupTime;
66 uint32_t FSMC_BusTurnAroundDuration;
71 uint32_t FSMC_CLKDivision;
75 uint32_t FSMC_DataLatency;
83 uint32_t FSMC_AccessMode;
96 uint32_t FSMC_DataAddressMux;
100 uint32_t FSMC_MemoryType;
104 uint32_t FSMC_MemoryDataWidth;
107 uint32_t FSMC_BurstAccessMode;
111 uint32_t FSMC_WaitSignalPolarity;
115 uint32_t FSMC_WrapMode;
119 uint32_t FSMC_WaitSignalActive;
124 uint32_t FSMC_WriteOperation;
127 uint32_t FSMC_WaitSignal;
131 uint32_t FSMC_ExtendedMode;
134 uint32_t FSMC_WriteBurst;
148 uint32_t FSMC_SetupTime;
154 uint32_t FSMC_WaitSetupTime;
160 uint32_t FSMC_HoldSetupTime;
167 uint32_t FSMC_HiZSetupTime;
183 uint32_t FSMC_Waitfeature;
186 uint32_t FSMC_MemoryDataWidth;
192 uint32_t FSMC_ECCPageSize;
195 uint32_t FSMC_TCLRSetupTime;
199 uint32_t FSMC_TARSetupTime;
214 uint32_t FSMC_Waitfeature;
217 uint32_t FSMC_TCLRSetupTime;
221 uint32_t FSMC_TARSetupTime;
244 #define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
245 #define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
246 #define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
247 #define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
255 #define FSMC_Bank2_NAND ((uint32_t)0x00000010)
256 #define FSMC_Bank3_NAND ((uint32_t)0x00000100)
264 #define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)
269 #define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
270 ((BANK) == FSMC_Bank1_NORSRAM2) || \
271 ((BANK) == FSMC_Bank1_NORSRAM3) || \
272 ((BANK) == FSMC_Bank1_NORSRAM4))
274 #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
275 ((BANK) == FSMC_Bank3_NAND))
277 #define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
278 ((BANK) == FSMC_Bank3_NAND) || \
279 ((BANK) == FSMC_Bank4_PCCARD))
281 #define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
282 ((BANK) == FSMC_Bank3_NAND) || \
283 ((BANK) == FSMC_Bank4_PCCARD))
293 #define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
294 #define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
295 #define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
296 ((MUX) == FSMC_DataAddressMux_Enable))
306 #define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
307 #define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
308 #define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
309 #define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
310 ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
311 ((MEMORY) == FSMC_MemoryType_NOR))
321 #define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
322 #define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
323 #define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
324 ((WIDTH) == FSMC_MemoryDataWidth_16b))
334 #define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
335 #define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
336 #define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
337 ((STATE) == FSMC_BurstAccessMode_Enable))
346 #define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
347 #define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
348 #define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
349 ((POLARITY) == FSMC_WaitSignalPolarity_High))
359 #define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
360 #define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
361 #define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
362 ((MODE) == FSMC_WrapMode_Enable))
372 #define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
373 #define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
374 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
375 ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
385 #define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
386 #define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
387 #define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
388 ((OPERATION) == FSMC_WriteOperation_Enable))
398 #define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
399 #define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
400 #define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
401 ((SIGNAL) == FSMC_WaitSignal_Enable))
410 #define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
411 #define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
413 #define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
414 ((MODE) == FSMC_ExtendedMode_Enable))
424 #define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
425 #define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
426 #define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
427 ((BURST) == FSMC_WriteBurst_Enable))
436 #define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
446 #define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
456 #define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
466 #define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
476 #define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
486 #define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
496 #define FSMC_AccessMode_A ((uint32_t)0x00000000)
497 #define FSMC_AccessMode_B ((uint32_t)0x10000000)
498 #define FSMC_AccessMode_C ((uint32_t)0x20000000)
499 #define FSMC_AccessMode_D ((uint32_t)0x30000000)
500 #define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
501 ((MODE) == FSMC_AccessMode_B) || \
502 ((MODE) == FSMC_AccessMode_C) || \
503 ((MODE) == FSMC_AccessMode_D))
521 #define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)
522 #define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)
523 #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
524 ((FEATURE) == FSMC_Waitfeature_Enable))
535 #define FSMC_ECC_Disable ((uint32_t)0x00000000)
536 #define FSMC_ECC_Enable ((uint32_t)0x00000040)
537 #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
538 ((STATE) == FSMC_ECC_Enable))
548 #define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
549 #define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
550 #define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
551 #define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
552 #define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
553 #define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
554 #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
555 ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
556 ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
557 ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
558 ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
559 ((SIZE) == FSMC_ECCPageSize_8192Bytes))
569 #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
579 #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
589 #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
599 #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
609 #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
619 #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
629 #define FSMC_IT_RisingEdge ((uint32_t)0x00000008)
630 #define FSMC_IT_Level ((uint32_t)0x00000010)
631 #define FSMC_IT_FallingEdge ((uint32_t)0x00000020)
632 #define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
633 #define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
634 ((IT) == FSMC_IT_Level) || \
635 ((IT) == FSMC_IT_FallingEdge))
644 #define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)
645 #define FSMC_FLAG_Level ((uint32_t)0x00000002)
646 #define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)
647 #define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
648 #define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
649 ((FLAG) == FSMC_FLAG_Level) || \
650 ((FLAG) == FSMC_FLAG_FallingEdge) || \
651 ((FLAG) == FSMC_FLAG_FEMPT))
653 #define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
689 void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
693 void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);