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#define | RCC_OFFSET (RCC_BASE - PERIPH_BASE) |
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#define | CR_OFFSET (RCC_OFFSET + 0x00) |
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#define | HSION_BitNumber 0x00 |
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#define | CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) |
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#define | PLLON_BitNumber 0x18 |
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#define | CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) |
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#define | CSSON_BitNumber 0x13 |
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#define | CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) |
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#define | CFGR_OFFSET (RCC_OFFSET + 0x04) |
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#define | USBPRE_BitNumber 0x16 |
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#define | CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4)) |
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#define | BDCR_OFFSET (RCC_OFFSET + 0x20) |
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#define | RTCEN_BitNumber 0x0F |
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#define | BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) |
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#define | BDRST_BitNumber 0x10 |
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#define | BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) |
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#define | CSR_OFFSET (RCC_OFFSET + 0x24) |
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#define | LSION_BitNumber 0x00 |
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#define | CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) |
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#define | CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) |
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#define | CR_HSEBYP_Set ((uint32_t)0x00040000) |
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#define | CR_HSEON_Reset ((uint32_t)0xFFFEFFFF) |
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#define | CR_HSEON_Set ((uint32_t)0x00010000) |
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#define | CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) |
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#define | CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF) |
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#define | CFGR_PLLMull_Mask ((uint32_t)0x003C0000) |
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#define | CFGR_PLLSRC_Mask ((uint32_t)0x00010000) |
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#define | CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000) |
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#define | CFGR_SWS_Mask ((uint32_t)0x0000000C) |
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#define | CFGR_SW_Mask ((uint32_t)0xFFFFFFFC) |
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#define | CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) |
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#define | CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0) |
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#define | CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) |
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#define | CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700) |
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#define | CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) |
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#define | CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800) |
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#define | CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) |
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#define | CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000) |
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#define | CSR_RMVF_Set ((uint32_t)0x01000000) |
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#define | FLAG_Mask ((uint8_t)0x1F) |
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#define | HSI_Value ((uint32_t)8000000) |
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#define | CIR_BYTE2_ADDRESS ((uint32_t)0x40021009) |
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#define | CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A) |
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#define | CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007) |
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#define | BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) |
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#define | HSEStartUp_TimeOut ((uint16_t)0x0500) |
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