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#define | PWR_OFFSET (PWR_BASE - PERIPH_BASE) |
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#define | CR_OFFSET (PWR_OFFSET + 0x00) |
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#define | DBP_BitNumber 0x08 |
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#define | CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) |
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#define | PVDE_BitNumber 0x04 |
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#define | CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) |
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#define | CSR_OFFSET (PWR_OFFSET + 0x04) |
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#define | EWUP_BitNumber 0x08 |
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#define | CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) |
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#define | CR_PDDS_Set ((uint32_t)0x00000002) |
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#define | CR_DS_Mask ((uint32_t)0xFFFFFFFC) |
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#define | CR_CWUF_Set ((uint32_t)0x00000004) |
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#define | CR_PLS_Mask ((uint32_t)0xFFFFFF1F) |
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#define | SCB_SysCtrl ((uint32_t)0xE000ED10) |
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#define | SysCtrl_SLEEPDEEP_Set ((uint32_t)0x00000004) |
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#define | SysCtrl_SLEEPDEEP_Reset ((uint32_t)0xFFFFFFFB) |
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