CAN_Private_Defines

Macros
#define	MCR_INRQ   ((uint32_t)0x00000001) /* Initialization request */
#define	MCR_SLEEP   ((uint32_t)0x00000002) /* Sleep mode request */
#define	MCR_TXFP   ((uint32_t)0x00000004) /* Transmit FIFO priority */
#define	MCR_RFLM   ((uint32_t)0x00000008) /* Receive FIFO locked mode */
#define	MCR_NART   ((uint32_t)0x00000010) /* No automatic retransmission */
#define	MCR_AWUM   ((uint32_t)0x00000020) /* Automatic wake up mode */
#define	MCR_ABOM   ((uint32_t)0x00000040) /* Automatic bus-off management */
#define	MCR_TTCM   ((uint32_t)0x00000080) /* time triggered communication */
#define	MCR_RESET   ((uint32_t)0x00008000) /* time triggered communication */
#define	MCR_DBF   ((uint32_t)0x00010000) /* software master reset */
#define	MSR_INAK   ((uint32_t)0x00000001) /* Initialization acknowledge */
#define	MSR_WKUI   ((uint32_t)0x00000008) /* Wake-up interrupt */
#define	MSR_SLAKI   ((uint32_t)0x00000010) /* Sleep acknowledge interrupt */
#define	TSR_RQCP0   ((uint32_t)0x00000001) /* Request completed mailbox0 */
#define	TSR_TXOK0   ((uint32_t)0x00000002) /* Transmission OK of mailbox0 */
#define	TSR_ABRQ0   ((uint32_t)0x00000080) /* Abort request for mailbox0 */
#define	TSR_RQCP1   ((uint32_t)0x00000100) /* Request completed mailbox1 */
#define	TSR_TXOK1   ((uint32_t)0x00000200) /* Transmission OK of mailbox1 */
#define	TSR_ABRQ1   ((uint32_t)0x00008000) /* Abort request for mailbox1 */
#define	TSR_RQCP2   ((uint32_t)0x00010000) /* Request completed mailbox2 */
#define	TSR_TXOK2   ((uint32_t)0x00020000) /* Transmission OK of mailbox2 */
#define	TSR_ABRQ2   ((uint32_t)0x00800000) /* Abort request for mailbox2 */
#define	TSR_TME0   ((uint32_t)0x04000000) /* Transmit mailbox 0 empty */
#define	TSR_TME1   ((uint32_t)0x08000000) /* Transmit mailbox 1 empty */
#define	TSR_TME2   ((uint32_t)0x10000000) /* Transmit mailbox 2 empty */
#define	RF0R_FULL0   ((uint32_t)0x00000008) /* FIFO 0 full */
#define	RF0R_FOVR0   ((uint32_t)0x00000010) /* FIFO 0 overrun */
#define	RF0R_RFOM0   ((uint32_t)0x00000020) /* Release FIFO 0 output mailbox */
#define	RF1R_FULL1   ((uint32_t)0x00000008) /* FIFO 1 full */
#define	RF1R_FOVR1   ((uint32_t)0x00000010) /* FIFO 1 overrun */
#define	RF1R_RFOM1   ((uint32_t)0x00000020) /* Release FIFO 1 output mailbox */
#define	ESR_EWGF   ((uint32_t)0x00000001) /* Error warning flag */
#define	ESR_EPVF   ((uint32_t)0x00000002) /* Error passive flag */
#define	ESR_BOFF   ((uint32_t)0x00000004) /* Bus-off flag */
#define	TMIDxR_TXRQ   ((uint32_t)0x00000001) /* Transmit mailbox request */
#define	FMR_FINIT   ((uint32_t)0x00000001) /* Filter init mode */
#define	INAK_TimeOut   ((uint32_t)0x0000FFFF)
#define	SLAK_TimeOut   ((uint32_t)0x0000FFFF)

Detailed Description