STM32F0 CPAL I2C bibliotheek  1.0
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stm32f0xx_i2c_cpal_hal.h
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1 
29 /* Define to prevent recursive inclusion -------------------------------------*/
30 #ifndef ___STM32F0XX_I2C_CPAL_HAL_H
31 #define ___STM32F0XX_I2C_CPAL_HAL_H
32 
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36 
37 /* Includes ------------------------------------------------------------------*/
38 /*========= STM32 Standard library files includes =========*/
39 #include "stm32f0xx.h"
40 #include "stm32f0xx_i2c.h"
41 #include "stm32f0xx_dma.h"
42 #include "stm32f0xx_gpio.h"
43 #include "stm32f0xx_rcc.h"
44 #include "stm32f0xx_misc.h"
45 
46 /*========= CPAL library files includes =========*/
47 #include "stm32f0xx_i2c_cpal.h"
48 
49 /* Exported types ------------------------------------------------------------*/
50 /* Exported constants --------------------------------------------------------*/
51 
52 /*======================================================================================================================================
53  CPAL Hardware Configuration
54 ========================================================================================================================================*/
55 
56 /* ------ Configure the communication device and all related peripherals ( GPIO Pin, DMA Channels,
57  NVIC Priority) with this file, by referring to configuration Sections:
58 
59  - Section 1 : Select the pins to be used for each device instance.
60 
61  - Section 2 : Select TX and RX DMA Channels (if DMA mode will be used).
62 
63  - Section 3 : Set device's Events, Errors and DMA Interrupts Priorities. */
64 
65 
66 /*-----------------------------------------------------------------------------------------------------------------------*/
67 /*-----------------------------------------------------------------------------------------------------------------------*/
68 
69 /* -- Section 1 : **** Device IO Pins Selection ****
70 
71  Description: This section allows user to choose IO Pins for each device if possible (in accordance with
72  used product: some products have only one possibility for the IO pins).
73  Each device instance (I2C1, I2C2 ..) has its specific defines: one for each Pin.
74  For each device instance, you will change existing defines with adequate IO Pins and Port
75  ( Refer to Product Pin mapping in related datasheet).*/
76 
77 /* To configure SCL and SDA Pin change these defines with adequate value :
78 
79 #define CPAL_I2C1_SCL_GPIO_PORT GPIOX (X : Name of the GPIO PORT (A,B,C,....))
80 #define CPAL_I2C1_SCL_GPIO_CLK RCC_APB2Periph_GPIOX (X : Name of the GPIO PORT (A,B,C,....))
81 #define CPAL_I2C1_SCL_GPIO_PIN GPIO_Pin_X (X : Pin number (1,2,3,....))
82 #define CPAL_I2C1_SCL_GPIO_PINSOURCE GPIO_PinSourceX (X : Pin number (1,2,3,....))
83 
84 #define CPAL_I2C1_SDA_GPIO_PORT GPIOX (X : Name of the GPIO PORT (A,B,C,....))
85 #define CPAL_I2C1_SDA_GPIO_CLK RCC_APB2Periph_GPIOX (X : Name of the GPIO PORT (A,B,C,....))
86 #define CPAL_I2C1_SDA_GPIO_PIN GPIO_Pin_X (X : Pin number (1,2,3,....))
87 #define CPAL_I2C1_SDA_GPIO_PINSOURCE GPIO_PinSourceX (X : Pin number (1,2,3,....)) */
88 
89 /* IO Pins selection possibilities
90 
91 |--------|---------|--------------|-----------|------------------|-------------------------|
92 | Device | I2C PIN | GPIO_PIN | GPIO_PORT | GPIO_PinSource | GPIO_CLK |
93 |--------|---------|--------------|-----------|------------------|-------------------------|
94 | | | GPIO_Pin_6 | GPIOB | GPIO_PinSource6 | RCC_AHBPeriph_GPIOB |
95 | | SCL |--------------|-----------|------------------|-------------------------|
96 | | | GPIO_Pin_8 | GPIOB | GPIO_PinSource8 | RCC_AHBPeriph_GPIOB |
97 | I2C1 |---------|--------------|-----------|------------------|-------------------------|
98 | | | GPIO_Pin_7 | GPIOB | GPIO_PinSource7 | RCC_AHBPeriph_GPIOB |
99 | | SDA |--------------|-----------|------------------|-------------------------|
100 | | | GPIO_Pin_9 | GPIOB | GPIO_PinSource9 | RCC_AHBPeriph_GPIOB |
101 |--------|---------|--------------|-----------|------------------|-------------------------|
102 | | | GPIO_Pin_10 | GPIOB | GPIO_PinSource10 | RCC_AHBPeriph_GPIOB |
103 | | SCL |--------------|-----------|------------------|-------------------------|
104 | | | GPIO_Pin_6 | GPIOF | GPIO_PinSource6 | RCC_AHBPeriph_GPIOF |
105 | I2C2 |---------|--------------|-----------|------------------|-------------------------|
106 | | | GPIO_Pin_11 | GPIOB | GPIO_PinSource11 | RCC_AHBPeriph_GPIOB |
107 | | SDA |--------------|-----------|------------------|-------------------------|
108 | | | GPIO_Pin_7 | GPIOF | GPIO_PinSource9 | RCC_AHBPeriph_GPIOF |
109 |--------|---------|--------------|-----------|------------------|-------------------------|
110 
111  */
112 
113 
114 /*----------- I2C1 Device -----------*/
115 
116 #define CPAL_I2C1_SCL_GPIO_PORT GPIOB
117 #define CPAL_I2C1_SCL_GPIO_CLK RCC_AHBPeriph_GPIOB
118 #define CPAL_I2C1_SCL_GPIO_PIN GPIO_Pin_6
119 #define CPAL_I2C1_SCL_GPIO_PINSOURCE GPIO_PinSource6
120 
121 #define CPAL_I2C1_SDA_GPIO_PORT GPIOB
122 #define CPAL_I2C1_SDA_GPIO_CLK RCC_AHBPeriph_GPIOB
123 #define CPAL_I2C1_SDA_GPIO_PIN GPIO_Pin_7
124 #define CPAL_I2C1_SDA_GPIO_PINSOURCE GPIO_PinSource7
125 
126 /*-----------I2C2 Device -----------*/
127 
128 #define CPAL_I2C2_SCL_GPIO_PORT GPIOB
129 #define CPAL_I2C2_SCL_GPIO_CLK RCC_AHBPeriph_GPIOB
130 #define CPAL_I2C2_SCL_GPIO_PIN GPIO_Pin_10
131 #define CPAL_I2C2_SCL_GPIO_PINSOURCE GPIO_PinSource10
132 
133 #define CPAL_I2C2_SDA_GPIO_PORT GPIOB
134 #define CPAL_I2C2_SDA_GPIO_CLK RCC_AHBPeriph_GPIOB
135 #define CPAL_I2C2_SDA_GPIO_PIN GPIO_Pin_11
136 #define CPAL_I2C2_SDA_GPIO_PINSOURCE GPIO_PinSource11
137 
138 /*-----------------------------------------------------------------------------------------------------------------------*/
139 /*-----------------------------------------------------------------------------------------------------------------------*/
140 
141 /* -- Section 2 : **** Device TX and RX DMA Channels Selection ****
142 
143  Description: This section allows user to choose TX and RX DMA Channels if possible (in accordance with
144  used product) for each device.
145  Each device instance (I2C1, I2C2 ..) has its specific defines: one for DMA TX Channel and
146  another one for DMA RX Channel.
147  For each device instance, you find all TX an RX DMA Channel possibilities ( Refer to Product
148  Reference Manual).*/
149 
150 /* DMA Channel selection possibilities
151 
152 |--------|---------|----------------|
153 | Device | Channel | DMA Channel |
154 |--------|---------|----------------|
155 | | TX | DMA1_Channel2 |
156 | I2C1 |---------|----------------|
157 | | RX | DMA1_Channel3 |
158 |--------|---------|----------------|
159 | | TX | DMA1_Channel4 |
160 | I2C2 |---------|----------------|
161 | | RX | DMA1_Channel5 |
162 |--------|---------|----------------|*/
163 
164 /* I2Cx TX and RX DMA channels for STM32F0XX family are fixed */
165 
166 /*----------- I2C1 Device -----------*/
167 #define CPAL_I2C1_DMA_TX_Channel DMA1_Channel2
168 #define CPAL_I2C1_DMA_RX_Channel DMA1_Channel3
169 
170 /*----------- I2C2 Device -----------*/
171 #define CPAL_I2C2_DMA_TX_Channel DMA1_Channel4
172 #define CPAL_I2C2_DMA_RX_Channel DMA1_Channel5
173 
174 /*-----------------------------------------------------------------------------------------------------------------------*/
175 /*-----------------------------------------------------------------------------------------------------------------------*/
176 
177 /* -- Section 3 : **** I2C and DMA Interrupts Priority Selection ****
178 
179  Description: This section allows user to select Interrupt Priority of I2C Event Interrupts and DMA Interrupts.
180 
181  Make sure that the following rules are always respected:
182  - I2C event and error interrupts should be interruptible (mainly, the timeout interrupt should
183  be able to interrupt all device ISR)
184  - I2C Error interrupt priority should be higher than Event interrupt
185  - The timeout mechanism interrupt priority should be the highest one and it should be able to
186  interrupt any other ISR.
187  - It is advised that DMA interrupts have higher priority than the device event interrupts.*/
188 
189 
190 /*----------- I2Cx Interrupt Priority -------------*/
191 
192 /*----------- I2C1 Device -----------*/
193 #define I2C1_IT_PRIO I2C1_IT_OFFSET_PREPRIO + 2 /* I2C1 IT PRIORITY */
194 #define I2C1_IT_DMA_PRIO I2C1_IT_OFFSET_PREPRIO + 0 /* I2C1 DMA PRIORITY */
195 
196 /*----------- I2C2 Device -----------*/
197 #define I2C2_IT_PRIO I2C2_IT_OFFSET_PREPRIO + 2 /* I2C2 IT PRIORITY */
198 #define I2C2_IT_DMA_PRIO I2C2_IT_OFFSET_PREPRIO + 0 /* I2C2 DMA PRIORITY */
199 
200 
201 /*-----------------------------------------------------------------------------------------------------------------------*/
202 /*-----------------------------------------------------------------------------------------------------------------------*/
203 
204 /*****END OF CPAL Hardware Configuration***************************************************************************************************/
205 
206  /* !WARNING!:
207  ---------
208  The following code should not be modified by user.
209  Any modification may cause Library dysfunction.
210  */
211 
212 /*========= Common Defines =========*/
213 
214 /* This define set the number of I2C devices that can be used with this product family */
215 #define CPAL_I2C_DEV_NUM 2
216 
217 /* This define is used to enable DMA Channel */
218 #define CPAL_DMA_CCR_EN DMA_CCR_EN
219 
220 /* This define is used to check if DMA interrupt option are enabled */
221 #define CPAL_OPT_DMA_IT_MASK ((uint32_t)0x00003F00)
222 
223 /* This define is used to check I2C errors (BERR, ARLO and OVR) */
224 #define CPAL_I2C_STATUS_ERR_MASK ((uint32_t)0x00000700)
226 /* This define is used to check I2C events (TXIS, RXNE, ADDR, NACKF, STOPF, TC and TCR) */
227 #define CPAL_I2C_STATUS_EVT_MASK ((uint16_t)0x0000000FE)
229 /* This define is used to check if DMA TX interrupt are selected */
230 #define CPAL_OPT_I2C_DMA_TX_IT_MASK ((uint32_t)0x00000700)
231 
232 /* This define is used to check if DMA RX interrupt are selected */
233 #define CPAL_OPT_I2C_DMA_RX_IT_MASK ((uint32_t)0x00003800)
234 
235  /* I2C Event Defines */
236 #define CPAL_I2C_EVT_ADDR I2C_ISR_ADDR
237 #define CPAL_I2C_EVT_STOP I2C_ISR_STOPF
238 #define CPAL_I2C_EVT_NACK I2C_ISR_NACKF
239 #define CPAL_I2C_EVT_RXNE I2C_ISR_RXNE
240 #define CPAL_I2C_EVT_TXIS I2C_ISR_TXIS
241 #define CPAL_I2C_EVT_TCR I2C_ISR_TCR
242 #define CPAL_I2C_EVT_TC I2C_ISR_TC
244 /*========= I2C1 specific defines (GPIO, PINs, Clocks and DMA) =========*/
245 
246 #define CPAL_I2C1_CLK RCC_APB1Periph_I2C1
247 #define CPAL_I2C1_TXDR ((uint32_t)0x40005428)
248 #define CPAL_I2C1_RXDR ((uint32_t)0x40005424)
249 #define CPAL_I2C1_AF GPIO_AF_1
250 
251 #define CPAL_I2C1_DMA DMA1
252 #define CPAL_I2C1_DMA_CLK RCC_AHBPeriph_DMA1
253 
254 #define CPAL_I2C1_IT_IRQn I2C1_IRQn
255 #define CPAL_I2C1_DMA_IRQn DMA1_Channel2_3_IRQn
256 
257 #define CPAL_I2C1_DMA_IRQHandler DMA1_Channel2_3_IRQHandler
258 
259 #define CPAL_I2C1_DMA_TX_TC_FLAG DMA1_FLAG_TC2
260 #define CPAL_I2C1_DMA_TX_HT_FLAG DMA1_FLAG_HT2
261 #define CPAL_I2C1_DMA_TX_TE_FLAG DMA1_FLAG_TE2
262 
263 #define CPAL_I2C1_DMA_RX_TC_FLAG DMA1_FLAG_TC3
264 #define CPAL_I2C1_DMA_RX_HT_FLAG DMA1_FLAG_HT3
265 #define CPAL_I2C1_DMA_RX_TE_FLAG DMA1_FLAG_TE3
266 
267 /*========= I2C2 specific defines (GPIO, PINs, Clocks and DMA) =========*/
268 
269 #define CPAL_I2C2_CLK RCC_APB1Periph_I2C2
270 #define CPAL_I2C2_TXDR ((uint32_t)0x40005828)
271 #define CPAL_I2C2_RXDR ((uint32_t)0x40005824)
272 #define CPAL_I2C2_AF GPIO_AF_1
273 
274 #define CPAL_I2C2_DMA DMA1
275 #define CPAL_I2C2_DMA_CLK RCC_AHBPeriph_DMA1
276 
277 #define CPAL_I2C2_IT_IRQn I2C2_IRQn
278 #define CPAL_I2C2_DMA_IRQn DMA1_Channel4_5_IRQn
279 
280 #define CPAL_I2C2_DMA_IRQHandler DMA1_Channel4_5_IRQHandler
281 
282 #define CPAL_I2C2_DMA_TX_TC_FLAG DMA1_FLAG_TC4
283 #define CPAL_I2C2_DMA_TX_HT_FLAG DMA1_FLAG_HT4
284 #define CPAL_I2C2_DMA_TX_TE_FLAG DMA1_FLAG_TE4
285 
286 #define CPAL_I2C2_DMA_RX_TC_FLAG DMA1_FLAG_TC5
287 #define CPAL_I2C2_DMA_RX_HT_FLAG DMA1_FLAG_HT5
288 #define CPAL_I2C2_DMA_RX_TE_FLAG DMA1_FLAG_TE5
289 
290 
291 /* Exported macro ------------------------------------------------------------*/
292 
293 /*========= Peripheral Clock Command =========*/
294 
295 #define __I2C_CLK_CMD(clk,cmd) RCC_APB1PeriphClockCmd((clk),(cmd))
296 
297 #define __I2C_RCC_RESET(clk) RCC_APB1PeriphResetCmd((clk),ENABLE);\
298  RCC_APB1PeriphResetCmd((clk),DISABLE)
299 
300 #define __I2C_GPIO_CLK_CMD(clk,cmd) RCC_AHBPeriphClockCmd((clk),(cmd))
301 
302 #define __DMA_CLK_CMD(clk,cmd) RCC_AHBPeriphClockCmd((clk),(cmd))
303 
304 #define __DMA_RESET_CMD(clk,cmd) RCC_AHBPeriphResetCmd((clk),(cmd))
305 
306 
307 /*========= DMA =========*/
308 
309 /* DMA channels enable/disable */
310 
311 #define __CPAL_I2C_HAL_ENABLE_DMATX(device) CPAL_I2C_DMA_TX_Channel[(device)]->CCR |= CPAL_DMA_CCR_EN
312 
313 #define __CPAL_I2C_HAL_DISABLE_DMATX(device) CPAL_I2C_DMA_TX_Channel[(device)]->CCR &= ~CPAL_DMA_CCR_EN
314 
315 #define __CPAL_I2C_HAL_ENABLE_DMARX(device) CPAL_I2C_DMA_RX_Channel[(device)]->CCR |= CPAL_DMA_CCR_EN
316 
317 #define __CPAL_I2C_HAL_DISABLE_DMARX(device) CPAL_I2C_DMA_RX_Channel[(device)]->CCR &= ~CPAL_DMA_CCR_EN
318 
319 /* DMA interrupts enable/disable */
320 
321 #define __I2C_HAL_ENABLE_DMATX_TCIT(device) CPAL_I2C_DMA_TX_Channel[(device)]->CCR |= DMA_IT_TC
322 
323 #define __I2C_HAL_ENABLE_DMATX_HTIT(device) CPAL_I2C_DMA_TX_Channel[(device)]->CCR |= DMA_IT_HT
324 
325 #define __I2C_HAL_ENABLE_DMATX_TEIT(device) CPAL_I2C_DMA_TX_Channel[(device)]->CCR |= DMA_IT_TE
326 
327 #define __I2C_HAL_ENABLE_DMARX_TCIT(device) CPAL_I2C_DMA_RX_Channel[(device)]->CCR |= DMA_IT_TC
328 
329 #define __I2C_HAL_ENABLE_DMARX_HTIT(device) CPAL_I2C_DMA_RX_Channel[(device)]->CCR |= DMA_IT_HT
330 
331 #define __I2C_HAL_ENABLE_DMARX_TEIT(device) CPAL_I2C_DMA_RX_Channel[(device)]->CCR |= DMA_IT_TE
332 
333 /* DMA interrupts flag management */
334 
335 #define __CPAL_I2C_HAL_GET_DMATX_IT(device) (uint32_t)(CPAL_I2C_DMA[(device)]->ISR & (CPAL_I2C_DMA_TX_TC_FLAG[(device)] \
336  | CPAL_I2C_DMA_TX_HT_FLAG[(device)] | CPAL_I2C_DMA_TX_TE_FLAG[(device)]))
337 
338 #define __CPAL_I2C_HAL_GET_DMATX_TCIT(device) (uint32_t)(CPAL_I2C_DMA[(device)]->ISR & CPAL_I2C_DMA_TX_TC_FLAG [(device)])
339 
340 #define __CPAL_I2C_HAL_GET_DMATX_HTIT(device) (uint32_t)(CPAL_I2C_DMA[(device)]->ISR & CPAL_I2C_DMA_TX_HT_FLAG [(device)])
341 
342 #define __CPAL_I2C_HAL_GET_DMATX_TEIT(device) (uint32_t)(CPAL_I2C_DMA[(device)]->ISR & CPAL_I2C_DMA_TX_TE_FLAG [(device)])
343 
344 #define __CPAL_I2C_HAL_GET_DMARX_IT(device) (uint32_t)(CPAL_I2C_DMA[(device)]->ISR & (CPAL_I2C_DMA_RX_TC_FLAG[(device)] \
345  | CPAL_I2C_DMA_RX_HT_FLAG[(device)] | CPAL_I2C_DMA_RX_TE_FLAG[(device)]))
346 
347 #define __CPAL_I2C_HAL_GET_DMARX_TCIT(device) (uint32_t)(CPAL_I2C_DMA[(device)]->ISR & CPAL_I2C_DMA_RX_TC_FLAG [(device)])
348 
349 #define __CPAL_I2C_HAL_GET_DMARX_HTIT(device) (uint32_t)(CPAL_I2C_DMA[(device)]->ISR & CPAL_I2C_DMA_RX_HT_FLAG [(device)])
350 
351 #define __CPAL_I2C_HAL_GET_DMARX_TEIT(device) (uint32_t)(CPAL_I2C_DMA[(device)]->ISR & CPAL_I2C_DMA_RX_TE_FLAG [(device)])
352 
353 #define __CPAL_I2C_HAL_CLEAR_DMATX_IT(device) CPAL_I2C_DMA[(device)]->IFCR = (CPAL_I2C_DMA_TX_TC_FLAG[(device)] \
354  | CPAL_I2C_DMA_TX_HT_FLAG[(device)] | CPAL_I2C_DMA_TX_TE_FLAG[(device)])
355 
356 #define __CPAL_I2C_HAL_CLEAR_DMARX_IT(device) CPAL_I2C_DMA[(device)]->IFCR = (CPAL_I2C_DMA_RX_TC_FLAG[(device)] \
357  | CPAL_I2C_DMA_RX_HT_FLAG[(device)] | CPAL_I2C_DMA_RX_TE_FLAG[(device)])
358 
359 /* Get DMA data counter */
360 
361 #define __CPAL_I2C_HAL_DMATX_GET_CNDT(device) (uint32_t)(CPAL_I2C_DMA_TX_Channel[(device)]->CNDTR)
362 
363 #define __CPAL_I2C_HAL_DMARX_GET_CNDT(device) (uint32_t)(CPAL_I2C_DMA_RX_Channel[(device)]->CNDTR)
364 
365 
366 /*========= I2C =========*/
367 
368 /* I2C enable/disable */
369 
370 #define __CPAL_I2C_HAL_ENABLE_DEV(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_PE
371 
372 #define __CPAL_I2C_HAL_DISABLE_DEV(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~I2C_CR1_PE
373 
374 /* I2C software reset */
375 
376 #define __CPAL_I2C_HAL_SWRST(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_SWRST; \
377  CPAL_I2C_DEVICE[(device)]->CR1 &= ~I2C_CR1_SWRST
378 
379 /* I2C Wakeup option */
380 
381 #define __CPAL_I2C_HAL_ENABLE_WAKEUP(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_WUPEN
382 
383 #define __CPAL_I2C_HAL_DISABLE_WAKEUP(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~I2C_CR1_WUPEN
384 
385 /* I2C interrupts enable/disable */
386 
387 #define __CPAL_I2C_HAL_DISABLE_ALLIT(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~(I2C_CR1_TXIE | I2C_CR1_RXIE | I2C_CR1_ADDRIE | \
388  I2C_CR1_STOPIE | I2C_CR1_TCIE | I2C_CR1_ERRIE | I2C_CR1_NACKIE)
389 
390 #define __CPAL_I2C_HAL_ENABLE_ERRIT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= (I2C_CR1_ERRIE | I2C_CR1_NACKIE)
391 
392 #define __CPAL_I2C_HAL_DISABLE_ERRIT(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~(I2C_CR1_ERRIE | I2C_CR1_NACKIE)
393 
394 
395 #define __CPAL_I2C_HAL_ENABLE_MASTER_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= (I2C_CR1_TCIE | I2C_CR1_STOPIE)
396 
397 #define __CPAL_I2C_HAL_DISABLE_MASTER_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~(I2C_CR1_TCIE | I2C_CR1_STOPIE)
398 
399 #define __CPAL_I2C_HAL_ENABLE_MASTER_TXIT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= (I2C_CR1_TCIE | I2C_CR1_STOPIE | I2C_CR1_TXIE)
400 
401 #define __CPAL_I2C_HAL_ENABLE_MASTER_RXIT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= (I2C_CR1_TCIE | I2C_CR1_STOPIE | I2C_CR1_RXIE)
402 
403 
404 #define __CPAL_I2C_HAL_ENABLE_SLAVE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= (I2C_CR1_ADDRIE | I2C_CR1_STOPIE)
405 
406 #define __CPAL_I2C_HAL_DISABLE_SLAVE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~(I2C_CR1_ADDRIE | I2C_CR1_STOPIE)
407 
408 #define __CPAL_I2C_HAL_ENABLE_SLAVE_TXIT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= (I2C_CR1_ADDRIE | I2C_CR1_STOPIE | I2C_CR1_TXIE)
409 
410 #define __CPAL_I2C_HAL_ENABLE_SLAVE_RXIT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= (I2C_CR1_ADDRIE | I2C_CR1_STOPIE | I2C_CR1_RXIE)
411 
412 
413 #define __CPAL_I2C_HAL_ENABLE_STOPIE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_STOPIE
414 
415 #define __CPAL_I2C_HAL_DISABLE_STOPIE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~I2C_CR1_STOPIE
416 
417 #define __CPAL_I2C_HAL_ENABLE_ADDRIE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_ADDRIE
418 
419 #define __CPAL_I2C_HAL_DISABLE_ADDRIE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~I2C_CR1_ADDRIE
420 
421 #define __CPAL_I2C_HAL_ENABLE_TCIE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_TCIE
422 
423 #define __CPAL_I2C_HAL_DISABLE_TCIE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~I2C_CR1_TCIE
424 
425 #define __CPAL_I2C_HAL_ENABLE_TXIE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_TXIE
426 
427 #define __CPAL_I2C_HAL_DISABLE_TXIE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~I2C_CR1_TXIE
428 
429 #define __CPAL_I2C_HAL_ENABLE_RXIE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_RXIE
430 
431 #define __CPAL_I2C_HAL_DISABLE_RXIE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~I2C_CR1_RXIE
432 
433 
434 /* I2C Addressing configuration */
435 
436 #define __CPAL_I2C_HAL_SADD_CONF(device,value) CPAL_I2C_DEVICE[(device)]->CR2 &= ~I2C_CR2_SADD; \
437  CPAL_I2C_DEVICE[(device)]->CR2 |= (uint32_t)((value) & 0x000003FF)
438 
439 #define __CPAL_I2C_HAL_OA2_CONF(device,value) CPAL_I2C_DEVICE[(device)]->OAR2 &= ~I2C_OAR2_OA2; \
440  CPAL_I2C_DEVICE[(device)]->OAR2 |= (uint32_t)((value) & 0x000000FE)
441 
442 #define __CPAL_I2C_HAL_OA2_MASK_CONF(device,value) CPAL_I2C_DEVICE[(device)]->OAR2 &= ~I2C_OAR2_OA2MSK; \
443  CPAL_I2C_DEVICE[(device)]->OAR2 |= (uint32_t)((value) << 8)
444 
445 #define __CPAL_I2C_HAL_ENABLE_OA2(device) CPAL_I2C_DEVICE[(device)]->OAR2 |= I2C_OAR2_OA2EN
446 
447 #define __CPAL_I2C_HAL_ENABLE_ADD10(device) CPAL_I2C_DEVICE[(device)]->CR2 |= I2C_CR2_ADD10
448 
449 #define __CPAL_I2C_HAL_DISABLE_ADD10(device) CPAL_I2C_DEVICE[(device)]->CR2 &= ~I2C_CR2_ADD10
450 
451 #define __CPAL_I2C_HAL_ENABLE_COMPLETE_HEAD10R(device) CPAL_I2C_DEVICE[(device)]->CR2 &= ~I2C_CR2_HEAD10R
452 
453 #define __CPAL_I2C_HAL_DISABLE_COMPLETE_HEAD10R(device) CPAL_I2C_DEVICE[(device)]->CR2 |= I2C_CR2_HEAD10R
454 
455 #define __CPAL_I2C_HAL_ENABLE_GENCALL(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_GCEN
456 
457 #define __CPAL_I2C_HAL_REQ_WRITE_TRANSFER(device) CPAL_I2C_DEVICE[(device)]->CR2 &= ~I2C_CR2_RD_WRN
458 
459 #define __CPAL_I2C_HAL_REQ_READ_TRANSFER(device) CPAL_I2C_DEVICE[(device)]->CR2 |= I2C_CR2_RD_WRN
460 
461 #define __CPAL_I2C_HAL_GET_OA1(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_OAR1_OA1)
462 
463 #define __CPAL_I2C_HAL_GET_OA2(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_OAR2_OA2)
464 
465 #define __CPAL_I2C_HAL_GET_OA2_MASK(device) (uint32_t)((CPAL_I2C_DEVICE[(device)]->ISR & I2C_OAR2_OA2MSK) >> 8)
466 
467 #define __CPAL_I2C_HAL_GET_ADDCODE(device) (uint32_t)((CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_ADDCODE) >> 17)
468 
469 #define __CPAL_I2C_HAL_GET_DIR(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_DIR)
470 
471 /* I2C misc configuration */
472 
473 #define __CPAL_I2C_HAL_CR2_UPDATE(device,value) CPAL_I2C_DEVICE[(device)]->CR2 = value
474 
475 #define __CPAL_I2C_HAL_ENABLE_TXDMAREQ(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_TXDMAEN
476 
477 #define __CPAL_I2C_HAL_DISABLE_TXDMAREQ(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~I2C_CR1_TXDMAEN
478 
479 #define __CPAL_I2C_HAL_ENABLE_RXDMAREQ(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_RXDMAEN
480 
481 #define __CPAL_I2C_HAL_DISABLE_RXDMAREQ(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~I2C_CR1_RXDMAEN
482 
483 #define __CPAL_I2C_HAL_ENABLE_NACK(device) CPAL_I2C_DEVICE[(device)]->CR2 |= I2C_CR2_NACK
484 
485 #define __CPAL_I2C_HAL_DISABLE_NACK(device) CPAL_I2C_DEVICE[(device)]->CR2 &= ~I2C_CR2_NACK
486 
487 #define __CPAL_I2C_HAL_ENABLE_AUTOEND(device) CPAL_I2C_DEVICE[(device)]->CR2 |= I2C_CR2_AUTOEND
488 
489 #define __CPAL_I2C_HAL_DISABLE_AUTOEND(device) CPAL_I2C_DEVICE[(device)]->CR2 &= ~I2C_CR2_AUTOEND
490 
491 #define __CPAL_I2C_HAL_ENABLE_RELOAD(device) CPAL_I2C_DEVICE[(device)]->CR2 |= I2C_CR2_RELOAD
492 
493 #define __CPAL_I2C_HAL_DISABLE_RELOAD(device) CPAL_I2C_DEVICE[(device)]->CR2 &= ~I2C_CR2_RELOAD
494 
495 #define __CPAL_I2C_HAL_ENABLE_NOSTRETCH(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_NOSTRETCH
496 
497 #define __CPAL_I2C_HAL_DISABLE_NOSTRETCH(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~I2C_CR1_NOSTRETCH
498 
499 #define __CPAL_I2C_HAL_START(device) CPAL_I2C_DEVICE[(device)]->CR2 |= I2C_CR2_START
500 
501 #define __CPAL_I2C_HAL_STOP(device) CPAL_I2C_DEVICE[(device)]->CR2 |= I2C_CR2_STOP
502 
503 /* I2C data management */
504 
505 #define __CPAL_I2C_HAL_RECEIVE(device) (uint8_t)(CPAL_I2C_DEVICE[(device)]->RXDR)
506 
507 #define __CPAL_I2C_HAL_SEND(device,value) CPAL_I2C_DEVICE[(device)]->TXDR = (uint8_t)((value))
508 
509 #define __CPAL_I2C_HAL_SET_NBYTES(device,value) CPAL_I2C_DEVICE[(device)]->CR2 &= ~I2C_CR2_NBYTES; \
510  CPAL_I2C_DEVICE[(device)]->CR2 |= (uint32_t)((uint32_t)(value) << 16)
511 
512 #define __CPAL_I2C_HAL_GET_NBYTES(device,value) (uint32_t)((CPAL_I2C_DEVICE[(device)]->CR2 & I2C_CR2_NBYTES) >> 16)
513 
514 #define __CPAL_I2C_HAL_CLEAR_NBYTES(device) CPAL_I2C_DEVICE[(device)]->CR2 &= ~I2C_CR2_NBYTES
515 
516 /* I2C flags management */
517 
518 #define __CPAL_I2C_HAL_GET_EVENT(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & CPAL_I2C_STATUS_EVT_MASK)
519 
520 #define __CPAL_I2C_HAL_GET_ERROR(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & CPAL_I2C_STATUS_ERR_MASK)
521 
522 #define __CPAL_I2C_HAL_GET_TXE(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_TXE)
523 
524 #define __CPAL_I2C_HAL_GET_TXIS(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_TXIS)
525 
526 #define __CPAL_I2C_HAL_GET_RXNE(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_RXNE)
527 
528 #define __CPAL_I2C_HAL_GET_ADDR(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_ADDR)
529 
530 #define __CPAL_I2C_HAL_GET_NACK(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_NACKF)
531 
532 #define __CPAL_I2C_HAL_GET_STOP(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_STOPF)
533 
534 #define __CPAL_I2C_HAL_GET_TC(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_TC)
535 
536 #define __CPAL_I2C_HAL_GET_TCR(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_TCR)
537 
538 #define __CPAL_I2C_HAL_GET_BERR(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_BERR)
539 
540 #define __CPAL_I2C_HAL_GET_ARLO(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_ARLO)
541 
542 #define __CPAL_I2C_HAL_GET_OVR(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_OVR)
543 
544 #define __CPAL_I2C_HAL_GET_BUSY(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_BUSY)
545 
546 #define __CPAL_I2C_HAL_CLEAR_ADDR(device) CPAL_I2C_DEVICE[(device)]->ICR = I2C_ICR_ADDRCF
547 
548 #define __CPAL_I2C_HAL_CLEAR_NACK(device) CPAL_I2C_DEVICE[(device)]->ICR = I2C_ICR_NACKCF
549 
550 #define __CPAL_I2C_HAL_CLEAR_STOP(device) CPAL_I2C_DEVICE[(device)]->ICR = I2C_ICR_STOPCF
551 
552 #define __CPAL_I2C_HAL_CLEAR_BERR(device) CPAL_I2C_DEVICE[(device)]->ICR = I2C_ICR_BERRCF
553 
554 #define __CPAL_I2C_HAL_CLEAR_ARLO(device) CPAL_I2C_DEVICE[(device)]->ICR = I2C_ICR_ARLOCF
555 
556 #define __CPAL_I2C_HAL_CLEAR_OVR(device) CPAL_I2C_DEVICE[(device)]->ICR = I2C_ICR_OVRCF
557 
558 /* Exported functions --------------------------------------------------------*/
559 
560 /*========= I2CX IRQHandler =========*/
561 
562 #ifdef CPAL_USE_I2C1
563  uint32_t I2C1_IRQHandler(void); /*<!I2C1 Interrupt Handler : handle Communication and errors of I2C1 Device */
564 
565 #endif /* CPAL_USE_I2C1 */
566 
567 #ifdef CPAL_USE_I2C2
568  uint32_t I2C2_IRQHandler(void); /*<!I2C1 Interrupt Handler : handle Communication and errors of I2C2 Device */
569 #endif /* CPAL_USE_I2C2 */
570 
571 
572 #ifdef CPAL_I2C_DMA_PROGMODEL
573 
574 /*========= DMA I2CX IRQHandler =========*/
575 
576 #ifdef CPAL_USE_I2C1
577  uint32_t CPAL_I2C1_DMA_IRQHandler(void); /*<!I2C1 DMA Interrupt Handler : handle data Transmission and reception with DMA */
578 #endif /* CPAL_USE_I2C1 */
579 
580 #ifdef CPAL_USE_I2C2
581  uint32_t CPAL_I2C2_DMA_IRQHandler(void); /*<!I2C2 DMA Interrupt Handler : handle data Transmission and reception with DMA */
582 #endif /* CPAL_USE_I2C2 */
583 
584 #endif /* CPAL_I2C_DMA_PROGMODEL */
585 
586 /*========= Hardware Abstraction Layer local =========*/
587 
588  void CPAL_I2C_HAL_CLKInit(CPAL_DevTypeDef Device); /*<!This function resets then enable the I2C device clock */
589 
590  void CPAL_I2C_HAL_CLKDeInit(CPAL_DevTypeDef Device); /*<!This function resets then disable the I2C device clock */
591 
592  void CPAL_I2C_HAL_GPIOInit(CPAL_DevTypeDef Device); /*<!This function configures the IO pins used by the I2C device */
593 
594  void CPAL_I2C_HAL_GPIODeInit(CPAL_DevTypeDef Device); /*<!This function deinitialize the IO pins used by the I2C device
595  (configured to their default state) */
596 
597 #ifdef CPAL_I2C_DMA_PROGMODEL
598  void CPAL_I2C_HAL_DMAInit(CPAL_DevTypeDef Device, CPAL_DirectionTypeDef Direction, uint32_t Options); /*<!This function enable the DMA clock and initialize
599  needed DMA Channels used by the I2C device*/
600 
601  void CPAL_I2C_HAL_DMATXConfig(CPAL_DevTypeDef Device,CPAL_TransferTypeDef* TransParameter, uint32_t Options); /*<!This function configures the DMA channel specific
602  for TX transfer */
603 
604  void CPAL_I2C_HAL_DMARXConfig(CPAL_DevTypeDef Device,CPAL_TransferTypeDef* TransParameter, uint32_t Options); /*<!This function configures the DMA channel specific
605  for RX transfer */
606 
607  void CPAL_I2C_HAL_DMADeInit(CPAL_DevTypeDef Device, CPAL_DirectionTypeDef Direction); /*<!This function deinitialize the DMA channel used
608  by I2C Device (Configure them to their default
609  values). DMA clock is not disabled */
610 #endif /* CPAL_I2C_DMA_PROGMODEL */
611 
612  void CPAL_I2C_HAL_ITInit(CPAL_DevTypeDef Device, uint32_t Options); /*<!This function configures NVIC and interrupts used
613  by I2C Device according to enabled options */
614 
615  void CPAL_I2C_HAL_ITDeInit(CPAL_DevTypeDef Device, uint32_t Options); /*<!This function deinitialize NVIC and interrupts used
616  by I2C Device */
617 
618 
619 #ifdef __cplusplus
620 }
621 #endif
622 
623 #endif /*___STM32F0XX_I2C_CPAL_HAL_H */
624 
625 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/